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Results:
1-7
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Results: 7
Authors:
TIWARI V
MALIK S
ASHAR P
Citation: V. Tiwari et al., GUARDED EVALUATION - PUSHING POWER MANAGEMENT TO LOGIC SYNTHESIS DESIGN/, IEEE transactions on computer-aided design of integrated circuits and systems, 17(10), 1998, pp. 1051-1060
Authors:
TIWARI V
ASHAR P
MALIK S
Citation: V. Tiwari et al., TECHNOLOGY MAPPING FOR LOW-POWER IN LOGIC SYNTHESIS, Integration, 20(3), 1996, pp. 243-268
Authors:
POTKONJAK M
ASHAR P
DEY S
MISAWA T
ROY RK
Citation: M. Potkonjak et al., SYNTHESIS TECHNIQUES FOR LOW-POWER DIGITAL DESIGNS, NEC research & development, 36(1), 1995, pp. 83-102
Authors:
ASHAR P
DEY S
MALIK S
Citation: P. Ashar et al., EXPLOITING MULTICYCLE FALSE PATHS IN THE PERFORMANCE OPTIMIZATION OF SEQUENTIAL LOGIC-CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(9), 1995, pp. 1067-1075
Authors:
ASHAR P
MALIK S
Citation: P. Ashar et S. Malik, FUNCTIONAL TIMING ANALYSIS USING ATPG, IEEE transactions on computer-aided design of integrated circuits and systems, 14(8), 1995, pp. 1025-1030
Authors:
RAHUNATHAN A
ASHAR P
MALIK S
Citation: A. Rahunathan et al., TEST-GENERATION FOR CYCLIC COMBINATIONAL-CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(11), 1995, pp. 1408-1414
Authors:
ASHAR P
DEVADAS S
KEUTZER K
Citation: P. Ashar et al., PATH-DELAY-FAULT TESTABILITY PROPERTIES OF MULTIPLEXOR-BASED NETWORKS, Integration, 15(1), 1993, pp. 1-23
Risultati:
1-7
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