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Results: 1-17 |
Results: 17
THEORY AND ALGORITHMS FOR FACE HYPERCUBE EMBEDDING
Authors: GOLDBERG EI VILLA T BRAYTON RK SANGIOVANNIVINCENTELLI AL
Citation: Ei. Goldberg et al., THEORY AND ALGORITHMS FOR FACE HYPERCUBE EMBEDDING, IEEE transactions on computer-aided design of integrated circuits and systems, 17(6), 1998, pp. 472-488
IMPLICIT COMPUTATION OF COMPATIBLE SETS FOR STATE MINIMIZATION OF ISFSMS
Authors: KAM T VILLA T BRAYTON RK SANGIOVANNIVINCENTELLI AL
Citation: T. Kam et al., IMPLICIT COMPUTATION OF COMPATIBLE SETS FOR STATE MINIMIZATION OF ISFSMS, IEEE transactions on computer-aided design of integrated circuits and systems, 16(7), 1997, pp. 657-676
EXPLICIT AND IMPLICIT ALGORITHMS FOR BINATE COVERING PROBLEMS
Authors: VILLA T KAM T BRAYTON RK SANGIOVANNIVINCENTELLI AL
Citation: T. Villa et al., EXPLICIT AND IMPLICIT ALGORITHMS FOR BINATE COVERING PROBLEMS, IEEE transactions on computer-aided design of integrated circuits and systems, 16(7), 1997, pp. 677-691
SYMBOLIC 2-LEVEL MINIMIZATION
Authors: VILLA T SALDANHA A BRAYTON RK SANGIOVANNIVINCENTELLI AL
Citation: T. Villa et al., SYMBOLIC 2-LEVEL MINIMIZATION, IEEE transactions on computer-aided design of integrated circuits and systems, 16(7), 1997, pp. 692-708
THEORY AND ALGORITHMS FOR STATE MINIMIZATION OF NONDETERMINISTIC FSMS
Authors: KAM T VILLA T BRAYTON RK SANGIOVANNIVINCENTELLI AL
Citation: T. Kam et al., THEORY AND ALGORITHMS FOR STATE MINIMIZATION OF NONDETERMINISTIC FSMS, IEEE transactions on computer-aided design of integrated circuits and systems, 16(11), 1997, pp. 1311-1322
COMBINATIONAL TEST-GENERATION USING SATISFIABILITY
Authors: STEPHAN P BRAYTON RK SANGIOVANNIVINCENTELLI AL
Citation: P. Stephan et al., COMBINATIONAL TEST-GENERATION USING SATISFIABILITY, IEEE transactions on computer-aided design of integrated circuits and systems, 15(9), 1996, pp. 1167-1176
PERMISSIBLE FUNCTIONS FOR MULTIOUTPUT COMPONENTS IN COMBINATIONAL LOGIC OPTIMIZATION
Authors: WATANABE Y GUERRA LM BRAYTON RK
Citation: Y. Watanabe et al., PERMISSIBLE FUNCTIONS FOR MULTIOUTPUT COMPONENTS IN COMBINATIONAL LOGIC OPTIMIZATION, IEEE transactions on computer-aided design of integrated circuits and systems, 15(7), 1996, pp. 732-744
VALID CLOCK FREQUENCIES AND THEIR COMPUTATION IN WAVEPIPELINED CIRCUITS
Authors: LAM WKC BRAYTON RK SANGIOVANNIVINCENTELLI AL
Citation: Wkc. Lam et al., VALID CLOCK FREQUENCIES AND THEIR COMPUTATION IN WAVEPIPELINED CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 15(7), 1996, pp. 791-807
NETWORK HIERARCHIES AND NODE MINIMIZATION
Authors: BRAYTON RK SENTOVICH EM
Citation: Rk. Brayton et Em. Sentovich, NETWORK HIERARCHIES AND NODE MINIMIZATION, IEICE transactions on information and systems, E78D(3), 1995, pp. 199-208
TESTING LANGUAGE CONTAINMENT FOR OMEGA-AUTOMATA USING BDDS
Authors: TOUATI HJ BRAYTON RK
Citation: Hj. Touati et Rk. Brayton, TESTING LANGUAGE CONTAINMENT FOR OMEGA-AUTOMATA USING BDDS, Information and computation, 118(1), 1995, pp. 101-109
DELAY-FAULT COVERAGE, TEST SET SIZE, AND PERFORMANCE TRADE-OFFS
Authors: LAM WK SALDANHA A BRAYTON RK SANGIOVANNIVINCENTELLI AL
Citation: Wk. Lam et al., DELAY-FAULT COVERAGE, TEST SET SIZE, AND PERFORMANCE TRADE-OFFS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(1), 1995, pp. 32-44
AN EFFICIENT HEURISTIC-PROCEDURE FOR SOLVING THE STATE ASSIGNMENT PROBLEM FOR EVENT-BASED SPECIFICATIONS
Authors: LAVAGNO L MOON CW BRAYTON RK SANGIOVANNIVINCENTELLI AL
Citation: L. Lavagno et al., AN EFFICIENT HEURISTIC-PROCEDURE FOR SOLVING THE STATE ASSIGNMENT PROBLEM FOR EVENT-BASED SPECIFICATIONS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(1), 1995, pp. 45-60
CIRCUIT STRUCTURE RELATIONS TO REDUNDANCY AND DELAY
Authors: SALDANHA A BRAYTON RK SANGIOVANNIVINCENTELLI AL
Citation: A. Saldanha et al., CIRCUIT STRUCTURE RELATIONS TO REDUNDANCY AND DELAY, IEEE transactions on computer-aided design of integrated circuits and systems, 13(7), 1994, pp. 875-883
SATISFACTION OF INPUT AND OUTPUT ENCODING CONSTRAINTS
Authors: SALDANHA A VILLA T BRAYTON RK SANGIOVANNIVINCENTELLI AL
Citation: A. Saldanha et al., SATISFACTION OF INPUT AND OUTPUT ENCODING CONSTRAINTS, IEEE transactions on computer-aided design of integrated circuits and systems, 13(5), 1994, pp. 589-602
PERFORMANCE OPTIMIZATION OF PIPELINED LOGIC-CIRCUITS USING PERIPHERALRETIMING AND RESYNTHESIS
Authors: MALIK S SINGH KJ BRAYTON RK SANGIOVANNIVINCENTELLI A
Citation: S. Malik et al., PERFORMANCE OPTIMIZATION OF PIPELINED LOGIC-CIRCUITS USING PERIPHERALRETIMING AND RESYNTHESIS, IEEE transactions on computer-aided design of integrated circuits and systems, 12(5), 1993, pp. 568-578
HEURISTIC MINIMIZATION OF MULTIPLE-VALUED RELATIONS
Authors: WATANABE Y BRAYTON RK
Citation: Y. Watanabe et Rk. Brayton, HEURISTIC MINIMIZATION OF MULTIPLE-VALUED RELATIONS, IEEE transactions on computer-aided design of integrated circuits and systems, 12(10), 1993, pp. 1458-1472
2-LEVEL MINIMIZATION OF MULTIVALUED FUNCTIONS WITH LARGE OFFSETS
Authors: MALIK AA BRAYTON RK NEWTON AR SANGIOVANNIVINCENTELLI AL
Citation: Aa. Malik et al., 2-LEVEL MINIMIZATION OF MULTIVALUED FUNCTIONS WITH LARGE OFFSETS, I.E.E.E. transactions on computers, 42(11), 1993, pp. 1325-1342
Risultati: 1-17 |