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Results: 1-11 |
Results: 11
A NOVEL DIMENSION-REDUCTION TECHNIQUE FOR THE CAPACITANCE EXTRACTION OF 3-D VLSI INTERCONNECTS
Authors: HONG W SUN WK ZHU ZH JI H SONG B DAI WWM
Citation: W. Hong et al., A NOVEL DIMENSION-REDUCTION TECHNIQUE FOR THE CAPACITANCE EXTRACTION OF 3-D VLSI INTERCONNECTS, IEEE transactions on microwave theory and techniques, 46(8), 1998, pp. 1037-1044
USEFUL-SKEW CLOCK ROUTING WITH GATE SIZING FOR LOW-POWER DESIGN
Authors: XI JGF DAI WWM
Citation: Jgf. Xi et Wwm. Dai, USEFUL-SKEW CLOCK ROUTING WITH GATE SIZING FOR LOW-POWER DESIGN, Journal of VLSI signal processing systems for signal, image, and video technology, 16(2-3), 1997, pp. 163-179
S-PARAMETER-BASED EXPERIMENTAL MODELING OF HIGH-Q-MCM INDUCTOR WITH EXPONENTIAL GRADIENT LEARNING ALGORITHM
Authors: ZHAO JS FRYE RC DAI WWM TAI KL
Citation: Js. Zhao et al., S-PARAMETER-BASED EXPERIMENTAL MODELING OF HIGH-Q-MCM INDUCTOR WITH EXPONENTIAL GRADIENT LEARNING ALGORITHM, IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, 20(3), 1997, pp. 202-210
ROUTABILITY ANALYSIS OF BIT-SERIAL PIPELINE DATAPATHS
Authors: ISSHIKI T DAI WWM KUNIEDA H
Citation: T. Isshiki et al., ROUTABILITY ANALYSIS OF BIT-SERIAL PIPELINE DATAPATHS, IEICE transactions on fundamentals of electronics, communications and computer science, E80A(10), 1997, pp. 1861-1870
A SILICON-ON-SILICON FIELD-PROGRAMMABLE MULTICHIP-MODULE (FPMCM) - INTEGRATING FPGA AND MCM TECHNOLOGIES (VOL 18, PG 601, 1995)
Authors: DARNAUER J ISSHIKI T GARAY P RAMIREZ J MAHESHWARI V DAI WWM
Citation: J. Darnauer et al., A SILICON-ON-SILICON FIELD-PROGRAMMABLE MULTICHIP-MODULE (FPMCM) - INTEGRATING FPGA AND MCM TECHNOLOGIES (VOL 18, PG 601, 1995), IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, 19(1), 1996, pp. 263-263
PLANAR CLOCK ROUTING FOR HIGH-PERFORMANCE CHIP AND PACKAGE CO-DESIGN
Authors: ZHU Q DAI WWM
Citation: Q. Zhu et Wwm. Dai, PLANAR CLOCK ROUTING FOR HIGH-PERFORMANCE CHIP AND PACKAGE CO-DESIGN, IEEE transactions on very large scale integration (VLSI) systems, 4(2), 1996, pp. 210-226
HIGH-SPEED CLOCK NETWORK SIZING OPTIMIZATION-BASED ON DISTRIBUTED RC AND LOSSY RLC INTERCONNECT MODELS
Authors: ZHU Q DAI WWM
Citation: Q. Zhu et Wwm. Dai, HIGH-SPEED CLOCK NETWORK SIZING OPTIMIZATION-BASED ON DISTRIBUTED RC AND LOSSY RLC INTERCONNECT MODELS, IEEE transactions on computer-aided design of integrated circuits and systems, 15(9), 1996, pp. 1106-1118
A SILICON-ON-SILICON FIELD-PROGRAMMABLE MULTICHIP-MODULE (FPMCM) - INTEGRATING FPGA AND MCM TECHNOLOGIES
Authors: DARNAUER J ISSHIKI T GARAY P RAMIREZ J MAHESHWARI V DAI WWM
Citation: J. Darnauer et al., A SILICON-ON-SILICON FIELD-PROGRAMMABLE MULTICHIP-MODULE (FPMCM) - INTEGRATING FPGA AND MCM TECHNOLOGIES, IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, 18(4), 1995, pp. 601-608
WAVE SPREADING EVALUATION OF INTERCONNECT SYSTEMS
Authors: LIAO HF DAI WWM
Citation: Hf. Liao et Wwm. Dai, WAVE SPREADING EVALUATION OF INTERCONNECT SYSTEMS, IEEE transactions on microwave theory and techniques, 43(10), 1995, pp. 2486-2491
MULTICHIP MODULES - INTRODUCTION
Authors: DAI WWM CHENG KT
Citation: Wwm. Dai et Kt. Cheng, MULTICHIP MODULES - INTRODUCTION, IEEE design & test of computers, 10(4), 1993, pp. 7-7
SURF - A RUBBER-BAND ROUTING SYSTEM FOR MULTICHIP MODULES
Authors: STAEPELAERE D JUE J DAYAN T DAI WWM
Citation: D. Staepelaere et al., SURF - A RUBBER-BAND ROUTING SYSTEM FOR MULTICHIP MODULES, IEEE design & test of computers, 10(4), 1993, pp. 18-26
Risultati: 1-11 |