AAAAAA

   
Results: 1-11 |
Results: 11
DESIGN METHODOLOGY AND OPTIMIZATION OF GATE-DRIVEN NMOS ESD PROTECTION CIRCUITS IN SUBMICRON CMOS PROCESSES
Authors: CHEN JZ AMERASEKERA EA DUVVURY C
Citation: Jz. Chen et al., DESIGN METHODOLOGY AND OPTIMIZATION OF GATE-DRIVEN NMOS ESD PROTECTION CIRCUITS IN SUBMICRON CMOS PROCESSES, I.E.E.E. transactions on electron devices, 45(12), 1998, pp. 2448-2456
MODELING MOS SNAPBACK AND PARASITIC BIPOLAR ACTION FOR CIRCUIT-LEVEL ESD AND HIGH-CURRENT SIMULATIONS
Authors: AMERASEKERA A CHANG MC DUVVURY C RAMASWAMY S
Citation: A. Amerasekera et al., MODELING MOS SNAPBACK AND PARASITIC BIPOLAR ACTION FOR CIRCUIT-LEVEL ESD AND HIGH-CURRENT SIMULATIONS, IEEE circuits and devices magazine, 13(2), 1997, pp. 7-10
ESD ISSUES FOR ADVANCED CMOS TECHNOLOGIES
Authors: DUVVURY C AMERASEKERA A
Citation: C. Duvvury et A. Amerasekera, ESD ISSUES FOR ADVANCED CMOS TECHNOLOGIES, Microelectronics and reliability, 36(7-8), 1996, pp. 907-924
SETTING THE TRAP FOR HOT CARRIERS
Authors: AUR S DUVVURY C HUNTER WR
Citation: S. Aur et al., SETTING THE TRAP FOR HOT CARRIERS, IEEE circuits and devices magazine, 11(4), 1995, pp. 18-24
THE IMPACT OF TECHNOLOGY SCALING ON ESD ROBUSTNESS AND PROTECTION CIRCUIT-DESIGN
Authors: AMERASEKERA A DUVVURY C
Citation: A. Amerasekera et C. Duvvury, THE IMPACT OF TECHNOLOGY SCALING ON ESD ROBUSTNESS AND PROTECTION CIRCUIT-DESIGN, IEEE transactions on components, packaging, and manufacturing technology. Part A, 18(2), 1995, pp. 314-320
ELECTRICAL OVERSTRESS AND ELECTROSTATIC DISCHARGE
Authors: DIAZ C KANG SM DUVVURY C
Citation: C. Diaz et al., ELECTRICAL OVERSTRESS AND ELECTROSTATIC DISCHARGE, IEEE transactions on reliability, 44(1), 1995, pp. 2-5
STUDIES OF EOS SUSCEPTIBILITY IN 0.6-MU-M NMOS ESD I O PROTECTION STRUCTURES/
Authors: DIAZ CH DUVVURY C KANG SM
Citation: Ch. Diaz et al., STUDIES OF EOS SUSCEPTIBILITY IN 0.6-MU-M NMOS ESD I O PROTECTION STRUCTURES/, Journal of electrostatics, 33(3), 1994, pp. 273-289
CIRCUIT-LEVEL ELECTROTHERMAL SIMULATION OF ELECTRICAL OVERSTRESS FAILURES IN ADVANCED MOS I O PROTECTION DEVICES/
Authors: DIAZ CH KANG SM DUVVURY C
Citation: Ch. Diaz et al., CIRCUIT-LEVEL ELECTROTHERMAL SIMULATION OF ELECTRICAL OVERSTRESS FAILURES IN ADVANCED MOS I O PROTECTION DEVICES/, IEEE transactions on computer-aided design of integrated circuits and systems, 13(4), 1994, pp. 482-493
SIMULATION OF ELECTRICAL OVERSTRESS THERMAL FAILURES IN INTEGRATED-CIRCUITS
Authors: DIAZ CH KANG SM DUVVURY C
Citation: Ch. Diaz et al., SIMULATION OF ELECTRICAL OVERSTRESS THERMAL FAILURES IN INTEGRATED-CIRCUITS, I.E.E.E. transactions on electron devices, 41(3), 1994, pp. 359-366
ELECTRICAL OVERSTRESS (EOS) POWER PROFILES - A GUIDELINE TO QUALIFY EOS HARDNESS OF SEMICONDUCTOR-DEVICES
Authors: DIAZ C KANG SM DUVVURY C WAGNER L
Citation: C. Diaz et al., ELECTRICAL OVERSTRESS (EOS) POWER PROFILES - A GUIDELINE TO QUALIFY EOS HARDNESS OF SEMICONDUCTOR-DEVICES, Journal of electrostatics, 31(2-3), 1993, pp. 161-176
ESD - A PERVASIVE RELIABILITY CONCERN FOR IC TECHNOLOGIES
Authors: DUVVURY C AMERASEKERA A
Citation: C. Duvvury et A. Amerasekera, ESD - A PERVASIVE RELIABILITY CONCERN FOR IC TECHNOLOGIES, Proceedings of the IEEE, 81(5), 1993, pp. 690-702
Risultati: 1-11 |