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Results: 1-10 |
Results: 10
FRC - A METHOD FOR EXTENDING THE RESOLUTION OF NYQUIST RATE CONVERTERS USING OVERSAMPLING
Authors: HARJANI R LEE TA
Citation: R. Harjani et Ta. Lee, FRC - A METHOD FOR EXTENDING THE RESOLUTION OF NYQUIST RATE CONVERTERS USING OVERSAMPLING, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 45(4), 1998, pp. 482-494
A BICMOS IMPLEMENTATION OF A 276MS S FORWARD EQUALIZER AND 200MS/S FDTS DETECTOR/
Authors: HARJANI R BARNETT R BUTENHOFF M
Citation: R. Harjani et al., A BICMOS IMPLEMENTATION OF A 276MS S FORWARD EQUALIZER AND 200MS/S FDTS DETECTOR/, IEEE transactions on magnetics, 34(1), 1998, pp. 160-165
ANALOG CIRCUIT OBSERVER BLOCKS
Authors: HARJANI R VINNAKOTA B
Citation: R. Harjani et B. Vinnakota, ANALOG CIRCUIT OBSERVER BLOCKS, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 44(3), 1997, pp. 154-163
FEASIBILITY AND PERFORMANCE REGION MODELING OF ANALOG AND DIGITAL CIRCUITS
Authors: HARJANI R SHAO JF
Citation: R. Harjani et Jf. Shao, FEASIBILITY AND PERFORMANCE REGION MODELING OF ANALOG AND DIGITAL CIRCUITS, Analog integrated circuits and signal processing, 10(1-2), 1996, pp. 23-43
ANALOG IMPLEMENTATION OF THE FDTS DF DETECTION ALGORITHM FOR MAGNETICRECORDING/
Authors: JAWORSKI RV HARJANI R
Citation: Rv. Jaworski et R. Harjani, ANALOG IMPLEMENTATION OF THE FDTS DF DETECTION ALGORITHM FOR MAGNETICRECORDING/, IEEE transactions on magnetics, 32(5), 1996, pp. 3944-3946
SYSTEM-LEVEL DESIGN FOR TEST OF FULLY DIFFERENTIAL ANALOG CIRCUITS
Authors: STESSMAN NJ VINNAKOTA B HARJANI R
Citation: Nj. Stessman et al., SYSTEM-LEVEL DESIGN FOR TEST OF FULLY DIFFERENTIAL ANALOG CIRCUITS, IEEE journal of solid-state circuits, 31(10), 1996, pp. 1526-1534
SELF-INITIALIZING MEMORY ELEMENTS
Authors: VINNAKOTA B HARJANI R
Citation: B. Vinnakota et R. Harjani, SELF-INITIALIZING MEMORY ELEMENTS, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 42(7), 1995, pp. 461-472
A LOW-POWER CMOS VGA FOR 50 MB S DISK-DRIVE READ CHANNELS/
Authors: HARJANI R
Citation: R. Harjani, A LOW-POWER CMOS VGA FOR 50 MB S DISK-DRIVE READ CHANNELS/, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 42(6), 1995, pp. 370-376
AN IMPROVED MODEL FOR THE SLEWING BEHAVIOR OF OPAMPS
Authors: WANG F HARJANI R
Citation: F. Wang et R. Harjani, AN IMPROVED MODEL FOR THE SLEWING BEHAVIOR OF OPAMPS, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 42(10), 1995, pp. 679-681
PARTIAL POSITIVE FEEDBACK FOR GAIN ENHANCEMENT OF LOW-POWER CMOS OTAS
Authors: WANG RT HARJANI R
Citation: Rt. Wang et R. Harjani, PARTIAL POSITIVE FEEDBACK FOR GAIN ENHANCEMENT OF LOW-POWER CMOS OTAS, Analog integrated circuits and signal processing, 8(1), 1995, pp. 21-35
Risultati: 1-10 |