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Results: 1-14 |
Results: 14
A Body-Effect-assisted NOR-type (BeNOR) multilevel flash memory
Authors: Wang, YS Tsai, HP Yang, ECS King, YC Chen, S Hsu, CCH
Citation: Ys. Wang et al., A Body-Effect-assisted NOR-type (BeNOR) multilevel flash memory, JPN J A P 1, 40(4B), 2001, pp. 2954-2957
New trap-assisted band-to-band tunneling induced gate current model for p-channel metal-oxide-semiconductor field effect transistors with sub-3 nm oxides
Authors: Lee, HM Liu, CJ Hsu, CW Liang, MS King, YC Hsu, CCH
Citation: Hm. Lee et al., New trap-assisted band-to-band tunneling induced gate current model for p-channel metal-oxide-semiconductor field effect transistors with sub-3 nm oxides, JPN J A P 1, 40(3A), 2001, pp. 1218-1221
Addressable failure site test structures (AFS-TS) for CMOS processes: Design guidelines, fault simulation, and implementation
Authors: Doong, KYY Hsieh, S Lin, SC Shen, B Cheng, JY Kwai, DM Hess, C Weiland, LH Hsu, CCH
Citation: Kyy. Doong et al., Addressable failure site test structures (AFS-TS) for CMOS processes: Design guidelines, fault simulation, and implementation, IEEE SEMIC, 14(4), 2001, pp. 338-355
Comprehensive study on a novel bidirectional tunneling program/erase NOR-type (BiNOR) 3-D flash memory cell
Authors: Chou, AHF Yang, ECS Liu, CJ Pong, HH Liaw, MC Chao, TS King, YC Hwang, HL Hsu, CCH
Citation: Ahf. Chou et al., Comprehensive study on a novel bidirectional tunneling program/erase NOR-type (BiNOR) 3-D flash memory cell, IEEE DEVICE, 48(7), 2001, pp. 1386-1393
A novel high-density and high-speed NAND-type electrical erasable programmable read only memory
Authors: Lin, FRL Lee, ML Lin, SY Boe, CH Yen, CP Wu, PH Wang, WS Ni, J Hsu, CCH
Citation: Frl. Lin et al., A novel high-density and high-speed NAND-type electrical erasable programmable read only memory, JPN J A P 1, 39(4B), 2000, pp. 2208-2214
A new bit-line-controlled self-convergent multilevel AND-type flash memory
Authors: Chou, AHF Yang, ECS Wong, WZ King, YC Hsu, CCH
Citation: Ahf. Chou et al., A new bit-line-controlled self-convergent multilevel AND-type flash memory, JPN J A P 1, 39(4B), 2000, pp. 2215-2218
Comprehensive study of a new self-convergent programming scheme for split gate flash memory
Authors: Chou, AHF Wong, WZ Yang, ECS Yao, YY Wang, YS King, YC Hsu, CCH
Citation: Ahf. Chou et al., Comprehensive study of a new self-convergent programming scheme for split gate flash memory, JPN J A P 1, 39(4B), 2000, pp. 2219-2222
Self-convergent programming scheme for multilevel p-channel flash memory
Authors: Hen, SJ Yang, CS Wang, YS Hsu, CCH
Citation: Sj. Hen et al., Self-convergent programming scheme for multilevel p-channel flash memory, JPN J A P 1, 39(1), 2000, pp. 1-7
Novel source-controlled self-verified programming for multilevel EEPROM's
Authors: Lin, FRL Lin, SY Lee, ML Boe, CH Yeh, CP Wu, PH Ni, J King, YC Hsu, CCH
Citation: Frl. Lin et al., Novel source-controlled self-verified programming for multilevel EEPROM's, IEEE DEVICE, 47(6), 2000, pp. 1166-1174
New self-adjusted dynamic source multilevel P-channel flash memory
Authors: Lin, RL Chang, T Wang, AC Hsu, CCH
Citation: Rl. Lin et al., New self-adjusted dynamic source multilevel P-channel flash memory, IEEE DEVICE, 47(4), 2000, pp. 841-847
New self-convergent programming method for multilevel AND flash memory
Authors: Yang, ECS Wong, WJ Wang, YS Shen, RSJ Hsu, CCH
Citation: Ecs. Yang et al., New self-convergent programming method for multilevel AND flash memory, JPN J A P 1, 38(4B), 1999, pp. 2210-2214
Novel bi-directional tunneling program erase NOR (BiNOR)-type flash EEPROM
Authors: Yang, ECS Liu, CJ Liaw, MC Chao, TS Hsu, CCH
Citation: Ecs. Yang et al., Novel bi-directional tunneling program erase NOR (BiNOR)-type flash EEPROM, IEEE DEVICE, 46(6), 1999, pp. 1294-1296
Mechanism of improved thermal stability of cobalt silicide formed on polysilicon gate by nitrogen implantation
Authors: Sun, WT Lee, HM Liaw, MC Hsu, CCH
Citation: Wt. Sun et al., Mechanism of improved thermal stability of cobalt silicide formed on polysilicon gate by nitrogen implantation, JPN J A P 1, 37(11), 1998, pp. 5854-5860
High speed F-N operated volatile memory cell with stacked plasma enhanced chemical vapor deposition (PECVD) nanocrystalline Si layer structure
Authors: Shen, SJ Lin, CJ Hsu, CCH
Citation: Sj. Shen et al., High speed F-N operated volatile memory cell with stacked plasma enhanced chemical vapor deposition (PECVD) nanocrystalline Si layer structure, JPN J A P 2, 37(12B), 1998, pp. L1517-L1519
Risultati: 1-14 |