Authors: FLANDRE D VIVIANI A EGGERMONT JP GENTINNE B JESPERS PGA

Citation: D. Flandre et al., IMPROVED SYNTHESIS OF GAIN-BOOSTED REGULATED-CASCODE CMOS STAGES USING SYMBOLIC ANALYSIS AND GM ID METHODOLOGY/, IEEE journal of solid-state circuits, 32(7), 1997, pp. 1006-1012

Authors: FLANDRE D FERREIRA LF JESPERS PGA COLINGE JP

Citation: D. Flandre et al., MODELING AND APPLICATION OF FULLY DEPLETED SOI MOSFETS FOR LOW-VOLTAGE, LOW-POWER ANALOG CMOS CIRCUITS, Solid-state electronics, 39(4), 1996, pp. 455-460

Authors: SILVEIRA F FLANDRE D JESPERS PGA

Citation: F. Silveira et al., A G(M) I-D BASED METHODOLOGY FOR THE DESIGN OF CMOS ANALOG CIRCUITS AND ITS APPLICATION TO THE SYNTHESIS OF A SILICON-ON-INSULATOR MICROPOWER OTA/, IEEE journal of solid-state circuits, 31(9), 1996, pp. 1314-1319

Authors: EGGERMONT JP DECEUSTER D FLANDRE D GENTINNE B JESPERS PGA COLINGE JP

Citation: Jp. Eggermont et al., DESIGN OF SOI CMOS OPERATIONAL-AMPLIFIERS FOR APPLICATIONS UP TO 300-DEGREES-C, IEEE journal of solid-state circuits, 31(2), 1996, pp. 179-186

Authors: MACQ D JESPERS PGA

Citation: D. Macq et Pga. Jespers, A 10-BIT PIPELINED SWITCHED-CURRENT A D CONVERTER/, IEEE journal of solid-state circuits, 29(8), 1994, pp. 967-971