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Results: 1-10 |
Results: 10
SYNDROME SIGNATURE IN OUTPUT COMPACTION FOR VLSI BUILT-IN SELF-TEST
Authors: DAS SR GOEL N JONE WB NAYAK AR
Citation: Sr. Das et al., SYNDROME SIGNATURE IN OUTPUT COMPACTION FOR VLSI BUILT-IN SELF-TEST, VLSI design (Yverdon), 7(2), 1998, pp. 191-201
DELAY-FAULT COVERAGE ENHANCEMENT USING VARIABLE OBSERVATION TIMES
Authors: JONE WB HO YP DAS SR
Citation: Wb. Jone et al., DELAY-FAULT COVERAGE ENHANCEMENT USING VARIABLE OBSERVATION TIMES, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 11(2), 1997, pp. 131-146
PGEN - A NOVEL-APPROACH TO SEQUENTIAL-CIRCUIT TEST-GENERATION
Authors: JONE WB SHAH N GLEASON A DAS SR
Citation: Wb. Jone et al., PGEN - A NOVEL-APPROACH TO SEQUENTIAL-CIRCUIT TEST-GENERATION, VLSI design, 4(3), 1996, pp. 149-165
PSEUDORANDOM TEST-LENGTH ANALYSIS USING DIFFERENTIAL SOLUTIONS
Authors: LI D JONE WB
Citation: D. Li et Wb. Jone, PSEUDORANDOM TEST-LENGTH ANALYSIS USING DIFFERENTIAL SOLUTIONS, IEEE transactions on computer-aided design of integrated circuits and systems, 15(7), 1996, pp. 815-825
REALIZING A HIGH MEASURE OF CONFIDENCE FOR DEFECT LEVEL ANALYSIS OF RANDOM TESTING
Authors: JONE WB GONDALIA P GUTJAHR A
Citation: Wb. Jone et al., REALIZING A HIGH MEASURE OF CONFIDENCE FOR DEFECT LEVEL ANALYSIS OF RANDOM TESTING, IEEE transactions on very large scale integration (VLSI) systems, 3(3), 1995, pp. 446-450
A COORDINATED CIRCUIT PARTITIONING AND TEST-GENERATION METHOD FOR PSEUDO-EXHAUSTIVE TESTING OF VLSI CIRCUITS
Authors: JONE WB PAPACHRISTOU CA
Citation: Wb. Jone et Ca. Papachristou, A COORDINATED CIRCUIT PARTITIONING AND TEST-GENERATION METHOD FOR PSEUDO-EXHAUSTIVE TESTING OF VLSI CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(3), 1995, pp. 374-384
TIMING OPTIMIZATION BY GATE RESIZING AND CRITICAL PATH IDENTIFICATION
Authors: FANG CL JONE WB
Citation: Cl. Fang et Wb. Jone, TIMING OPTIMIZATION BY GATE RESIZING AND CRITICAL PATH IDENTIFICATION, IEEE transactions on computer-aided design of integrated circuits and systems, 14(2), 1995, pp. 201-217
CACOP - A RANDOM PATTERN TESTABILITY ANALYZER
Authors: JONE WB DAS SR
Citation: Wb. Jone et Sr. Das, CACOP - A RANDOM PATTERN TESTABILITY ANALYZER, IEEE transactions on systems, man, and cybernetics, 25(5), 1995, pp. 865-871
ON TESTING OF SEQUENTIAL-MACHINES USING CIRCUIT DECOMPOSITION AND STOCHASTIC MODELING
Authors: DAS SR JONE WB NAYAK AR CHOI I
Citation: Sr. Das et al., ON TESTING OF SEQUENTIAL-MACHINES USING CIRCUIT DECOMPOSITION AND STOCHASTIC MODELING, IEEE transactions on systems, man, and cybernetics, 25(3), 1995, pp. 489-504
MULTIPLE-FAULT DETECTION IN PARITY CHECKERS
Authors: JONE WB WU CJ
Citation: Wb. Jone et Cj. Wu, MULTIPLE-FAULT DETECTION IN PARITY CHECKERS, I.E.E.E. transactions on computers, 43(9), 1994, pp. 1096-1099
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