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Results: 1-15 |
Results: 15
Efficient optimization by modifying the objective function: Applications to timing-driven VLSI layout
Authors: Baldick, R Kahng, AB Kennings, A Markov, IL
Citation: R. Baldick et al., Efficient optimization by modifying the objective function: Applications to timing-driven VLSI layout, IEEE CIRC-I, 48(8), 2001, pp. 947-956
Roadmaps and visions for design and test
Authors: Joyner, WH Kahng, AB
Citation: Wh. Joyner et Ab. Kahng, Roadmaps and visions for design and test, IEEE DES T, 18(6), 2001, pp. 4-5
Toward accurate models of achievable routing
Authors: Kahng, AB Mantik, S Stroobandt, D
Citation: Ab. Kahng et al., Toward accurate models of achievable routing, IEEE COMP A, 20(5), 2001, pp. 648-659
Constraint-based watermarking techniques for design IP protection
Authors: Kahng, AB Lach, J Mangione-Smith, WH Mantik, S Markov, IL Potkonjak, M Tucker, P Wang, HJ Wolfe, G
Citation: Ab. Kahng et al., Constraint-based watermarking techniques for design IP protection, IEEE COMP A, 20(10), 2001, pp. 1236-1252
Limitations and challenges of computer-aided design technology for CMOS VLSI
Authors: Bryant, RE Cheng, KT Kahng, AB Keutzer, K Maly, W Newton, R Pileggi, L Rabaey, JM Sangiovanni-Vincentelli, A
Citation: Re. Bryant et al., Limitations and challenges of computer-aided design technology for CMOS VLSI, P IEEE, 89(3), 2001, pp. 341-365
Iterative partitioning with varying node weights
Authors: Caldwell, AE Kahng, AB Markov, IL
Citation: Ae. Caldwell et al., Iterative partitioning with varying node weights, VLSI DESIGN, 11(3), 2000, pp. 249-258
System-level interconnect prediction
Authors: Kahng, AB Stroobandt, D
Citation: Ab. Kahng et D. Stroobandt, System-level interconnect prediction, IEEE VLSI, 8(6), 2000, pp. 637-638
Optimal phase conflict removal for layout of dark field alternating phase shifting masks
Authors: Berman, P Kahng, AB Vidhani, D Wang, HJ Zelikovsky, A
Citation: P. Berman et al., Optimal phase conflict removal for layout of dark field alternating phase shifting masks, IEEE COMP A, 19(2), 2000, pp. 175-187
Hypergraph partitioning with fixed vertices
Authors: Alpert, CJ Caldwell, AE Kahng, AB Markov, IL
Citation: Cj. Alpert et al., Hypergraph partitioning with fixed vertices, IEEE COMP A, 19(2), 2000, pp. 267-272
Optimal partitioners and end-case placers for standard-cell layout
Authors: Caldwell, AE Kahng, AB Markov, IL
Citation: Ae. Caldwell et al., Optimal partitioners and end-case placers for standard-cell layout, IEEE COMP A, 19(11), 2000, pp. 1304-1313
Spectral partitioning with multiple eigenvectors
Authors: Alpert, CJ Kahng, AB Yao, SZ
Citation: Cj. Alpert et al., Spectral partitioning with multiple eigenvectors, DISCR APP M, 90(1-3), 1999, pp. 3-26
Tuning strategies for global interconnects in high-performance deep-submicron ICs
Authors: Kahng, AB Muddu, S Sarto, E
Citation: Ab. Kahng et al., Tuning strategies for global interconnects in high-performance deep-submicron ICs, VLSI DESIGN, 10(1), 1999, pp. 21-34
Analytical engines are unnecessary in top-down partitioning-based placement
Authors: Alpert, CJ Caldwell, AE Chan, TF Huang, DJH Kahng, AB Markov, IL Moroz, MS
Citation: Cj. Alpert et al., Analytical engines are unnecessary in top-down partitioning-based placement, VLSI DESIGN, 10(1), 1999, pp. 99-116
On wirelength estimations for row-based placement
Authors: Caldwell, AE Kahng, AB Mantik, S Markov, IL Zelikovsky, A
Citation: Ae. Caldwell et al., On wirelength estimations for row-based placement, IEEE COMP A, 18(9), 1999, pp. 1265-1278
Filling algorithms and analyses for layout density control
Authors: Kahng, AB Robins, G Singh, A Zelikovsky, A
Citation: Ab. Kahng et al., Filling algorithms and analyses for layout density control, IEEE COMP A, 18(4), 1999, pp. 445-462
Risultati: 1-15 |