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Results: 1-19 |
Results: 19
4-QUADRANT ANALOG CMOS MULTIPLIER CELL FOR VLSI SIGNAL AND INFORMATION-PROCESSING
Authors: LAU KT LEE ST ONG VKS
Citation: Kt. Lau et al., 4-QUADRANT ANALOG CMOS MULTIPLIER CELL FOR VLSI SIGNAL AND INFORMATION-PROCESSING, IEE proceedings. Circuits, devices and systems, 145(2), 1998, pp. 132-134
THE OPTIMIZATION OF SORPTION SENSOR ARRAYS FOR USE IN AMBIENT CONDITIONS
Authors: LAU KT MICKLEFIELD J SLATER JM
Citation: Kt. Lau et al., THE OPTIMIZATION OF SORPTION SENSOR ARRAYS FOR USE IN AMBIENT CONDITIONS, Sensors and actuators. B, Chemical, 50(1), 1998, pp. 69-79
LOW-POWER SWITCHED OUTPUT ADIABATIC LOGIC
Authors: WANG WY LAU KT
Citation: Wy. Wang et Kt. Lau, LOW-POWER SWITCHED OUTPUT ADIABATIC LOGIC, International journal of electronics, 84(6), 1998, pp. 589-594
A CMOS WINNER-TAKES-ALL CIRCUIT FOR SELF-ORGANIZING NEURAL NETWORKS
Authors: LAU KT LEE ST
Citation: Kt. Lau et St. Lee, A CMOS WINNER-TAKES-ALL CIRCUIT FOR SELF-ORGANIZING NEURAL NETWORKS, International journal of electronics, 84(2), 1998, pp. 131-136
PASS-TRANSISTOR ADIABATIC LOGIC WITH NMOS PULL-DOWN CONFIGURATION
Authors: LIU F LAU KT
Citation: F. Liu et Kt. Lau, PASS-TRANSISTOR ADIABATIC LOGIC WITH NMOS PULL-DOWN CONFIGURATION, Electronics Letters, 34(8), 1998, pp. 739-741
4-PHASE IMPROVED ADIABATIC PSEUDO-DOMINO LOGIC
Authors: LAU KT LIU F
Citation: Kt. Lau et F. Liu, 4-PHASE IMPROVED ADIABATIC PSEUDO-DOMINO LOGIC, Electronics Letters, 34(4), 1998, pp. 343-344
IMPROVED STRUCTURE FOR EFFICIENT CHARGE RECOVERY LOGIC
Authors: LIU F LAU KT
Citation: F. Liu et Kt. Lau, IMPROVED STRUCTURE FOR EFFICIENT CHARGE RECOVERY LOGIC, Electronics Letters, 34(18), 1998, pp. 1731-1732
CMOS DESIGN OF THE HAO-VANDEWALLE MODEL OF NEURAL ASSOCIATIVE MEMORY
Authors: LAU KT LEE ST LIU PC
Citation: Kt. Lau et al., CMOS DESIGN OF THE HAO-VANDEWALLE MODEL OF NEURAL ASSOCIATIVE MEMORY, International journal of electronics, 83(1), 1997, pp. 79-90
A PROGRAMMABLE CMOS GAUSSIAN SYNAPSE FOR ANALOG VLSI NEURAL NETWORKS
Authors: LAU KT LEE ST
Citation: Kt. Lau et St. Lee, A PROGRAMMABLE CMOS GAUSSIAN SYNAPSE FOR ANALOG VLSI NEURAL NETWORKS, International journal of electronics, 83(1), 1997, pp. 91-98
IMPROVED ADIABATIC PSEUDO-DOMINO LOGIC FAMILY
Authors: LAU KT LIU F
Citation: Kt. Lau et F. Liu, IMPROVED ADIABATIC PSEUDO-DOMINO LOGIC FAMILY, Electronics Letters, 33(25), 1997, pp. 2113-2114
TRANSMISSION GATE-INTERFACED APDL DESIGN
Authors: LAU KT WANG WY
Citation: Kt. Lau et Wy. Wang, TRANSMISSION GATE-INTERFACED APDL DESIGN, Electronics Letters, 32(4), 1996, pp. 317-318
LOW-POWER DUAL-PORT CMOS SRAM MACRO DESIGN
Authors: WANG H LIU PC LAU KT
Citation: H. Wang et al., LOW-POWER DUAL-PORT CMOS SRAM MACRO DESIGN, Electronics Letters, 32(15), 1996, pp. 1354-1356
DESIGN AND IMPLEMENTATION OF AN FPGA TRANSPONDER
Authors: TAN BH TAN E LAU KT MAR SC
Citation: Bh. Tan et al., DESIGN AND IMPLEMENTATION OF AN FPGA TRANSPONDER, Microprocessors and microsystems, 19(5), 1995, pp. 255-259
A PC-BASED MPEG COMPRESSED DATA DECODER
Authors: OOI TH LAU KT LIM CH YEO KS YIP YE POK KA WONG CJ
Citation: Th. Ooi et al., A PC-BASED MPEG COMPRESSED DATA DECODER, IEEE transactions on consumer electronics, 41(4), 1995, pp. 1169-1173
ADIABATIC PSEUDO-DOMINO LOGIC
Authors: WANG WY LAU KT
Citation: Wy. Wang et Kt. Lau, ADIABATIC PSEUDO-DOMINO LOGIC, Electronics Letters, 31(23), 1995, pp. 1982-1983
LOW-POWER BUILDING-BLOCK FOR ARTIFICIAL NEURAL NETWORKS
Authors: LEE ST LAU KT
Citation: St. Lee et Kt. Lau, LOW-POWER BUILDING-BLOCK FOR ARTIFICIAL NEURAL NETWORKS, Electronics Letters, 31(19), 1995, pp. 1618-1619
4-QUADRANT CMOS ANALOG MULTIPLIER FOR ARTIFICIAL NEURAL NETWORKS
Authors: LEE ST LAU KT SIEK L
Citation: St. Lee et al., 4-QUADRANT CMOS ANALOG MULTIPLIER FOR ARTIFICIAL NEURAL NETWORKS, Electronics Letters, 31(1), 1995, pp. 48-49
A PC-CONTROLLED MULTIPLE WINDOW DISPLAY CARD FOR TV
Authors: OOI TH LAU KT LIM CH LIM SW LING KH POK KA WONG CJ
Citation: Th. Ooi et al., A PC-CONTROLLED MULTIPLE WINDOW DISPLAY CARD FOR TV, IEEE transactions on consumer electronics, 40(4), 1994, pp. 869-878
DSP-BASED HIGH-SPEED MEASUREMENT SYSTEM FOR HYBRID OSCILLATORS
Authors: OOI TH LAU KT LIM CH YEO A
Citation: Th. Ooi et al., DSP-BASED HIGH-SPEED MEASUREMENT SYSTEM FOR HYBRID OSCILLATORS, British Journal of Non-Destructive Testing, 35(8), 1993, pp. 439-441
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