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Results:
1-15
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Results: 15
Authors:
Macii, A
Macii, E
Poncino, M
Scarsi, R
Citation: A. Macii et al., Stream synthesis for efficient power simulation based on spectral transforms, IEEE VLSI, 9(3), 2001, pp. 417-426
Authors:
Kruse, L
Schmidt, E
Jochens, G
Stammermann, A
Schulz, A
Macii, E
Nebel, W
Citation: L. Kruse et al., Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs, IEEE VLSI, 9(1), 2001, pp. 3-14
Authors:
Macii, E
Citation: E. Macii, Dynamic power management of electronic systems, IEEE DES T, 18(2), 2001, pp. 6-9
Authors:
Benini, L
De Micheli, G
Lioy, A
Macii, E
Odasso, G
Poncino, M
Citation: L. Benini et al., Synthesis of power-managed sequential components based on computational kernel extraction, IEEE COMP A, 20(9), 2001, pp. 1118-1131
Authors:
Kumthekar, B
Benini, L
Macii, E
Somenzi, F
Citation: B. Kumthekar et al., Power optimisation of FPGA-based designs without rewiring, IEE P-COM D, 147(3), 2000, pp. 167-174
Authors:
Bahar, RI
Lampe, ET
Macii, E
Citation: Ri. Bahar et al., Power optimization of technology-dependent circuits based on symbolic computation of logic implications, ACM T DES A, 5(3), 2000, pp. 267-293
Authors:
Benini, L
De Micheli, D
Macii, A
Macii, E
Poncino, M
Scarsi, R
Citation: L. Benini et al., Glitch power minimization by selective gate freezing, IEEE VLSI, 8(3), 2000, pp. 287-298
Increasing energy efficiency of embedded systems by application-specific memory hierarchy generation
Authors:
Benini, L
Macii, A
Macii, E
Poncino, M
Citation: L. Benini et al., Increasing energy efficiency of embedded systems by application-specific memory hierarchy generation, IEEE DES T, 17(2), 2000, pp. 74-85
Authors:
Benini, L
Macii, A
Macii, E
Poncino, M
Scarsi, R
Citation: L. Benini et al., Architectures and synthesis algorithms for power-efficient bus interfaces, IEEE COMP A, 19(9), 2000, pp. 969-980
Authors:
Ferrandi, F
Fummi, F
Macii, E
Poncino, M
Sciuto, D
Citation: F. Ferrandi et al., Symbolic optimization of interacting controllers based on redundancy identification and removal, IEEE COMP A, 19(7), 2000, pp. 760-772
Authors:
Benini, L
De Micheli, G
Macii, E
Poncino, M
Scarsi, R
Citation: L. Benini et al., A multilevel engine for fast power simulation of realistic input streams, IEEE COMP A, 19(4), 2000, pp. 459-472
Authors:
Baldi, M
Macii, A
Macii, E
Poncino, R
Citation: M. Baldi et al., Application of symbolic FSM Markovian analysis to protocol verification, IEE P-COM D, 146(5), 1999, pp. 221-226
Authors:
Benini, L
De Micheli, G
Macii, A
Macii, E
Poncino, M
Citation: L. Benini et al., Automatic selection of instruction op-codes of low-power core processors, IEE P-COM D, 146(4), 1999, pp. 173-178
Authors:
Benini, L
De Micheli, G
Lioy, A
Macii, E
Odasso, G
Poncino, M
Citation: L. Benini et al., Automatic synthesis of large telescopic units based on near-minimum timed supersetting, IEEE COMPUT, 48(8), 1999, pp. 769-779
Authors:
Macii, E
Pedram, M
Somenzi, F
Citation: E. Macii et al., High-level power modeling, estimation, and optimization, IEEE COMP A, 17(11), 1998, pp. 1061-1079
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1-15
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