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Results: 1-11 |
Results: 11
Ultrathin gate oxide CMOS with nondoped selective epitaxial Si channel layer
Authors: Momose, HS Ohguro, T Morifuji, E Sugaya, H Nakamura, S Iwai, H
Citation: Hs. Momose et al., Ultrathin gate oxide CMOS with nondoped selective epitaxial Si channel layer, IEEE DEVICE, 48(6), 2001, pp. 1136-1144
Cutoff frequency and propagation delay time of 1.5-nm gate oxide CMOS
Authors: Momose, HS Morifuji, E Yoshitomi, T Ohguro, T Saito, M Iwai, H
Citation: Hs. Momose et al., Cutoff frequency and propagation delay time of 1.5-nm gate oxide CMOS, IEEE DEVICE, 48(6), 2001, pp. 1165-1174
A single-chip CMOS transceiver front-end for DCS-1800 wireless communications
Authors: Steyaert, M Borremans, M Janssens, J De Muer, B Itoh, N Craninckx, J Crols, J Morifuji, E Momose, HS Sansen, W
Citation: M. Steyaert et al., A single-chip CMOS transceiver front-end for DCS-1800 wireless communications, ANALOG IN C, 24(2), 2000, pp. 83-99
Hot-carrier reliability of ultra-thin gate oxide CMOS
Authors: Momose, HS Nakamura, S Ohguro, T Yoshitomi, T Morifuji, E Morimoto, T Katsumata, Y Iwai, H
Citation: Hs. Momose et al., Hot-carrier reliability of ultra-thin gate oxide CMOS, SOL ST ELEC, 44(11), 2000, pp. 2035-2044
Power Si-MOSFET operating with high efficiency under low supply voltage
Authors: Ohguro, T Saito, M Morifuji, E Murakami, K Matsuzaki, K Yoshitomi, T Morimoto, T Momose, HS Katsumata, Y Iwai, H
Citation: T. Ohguro et al., Power Si-MOSFET operating with high efficiency under low supply voltage, IEEE DEVICE, 47(12), 2000, pp. 2385-2391
An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs
Authors: Goo, JS Choi, CH Danneville, F Morifuji, E Momose, HS Yu, ZP Iwai, H Lee, TH Dutton, RW
Citation: Js. Goo et al., An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs, IEEE DEVICE, 47(12), 2000, pp. 2410-2419
Thermal stability of CoSi2 film for CMOS salicide
Authors: Ohguro, T Saito, M Morifuji, E Yoshitomi, T Morimoto, T Momose, HS Katsumata, Y Iwai, H
Citation: T. Ohguro et al., Thermal stability of CoSi2 film for CMOS salicide, IEEE DEVICE, 47(11), 2000, pp. 2208-2213
A high performance 0.15 mu m buried channel pMOSFET with extremely shallowcounter doped channel region using solid phase diffusion
Authors: Yoshitomi, T Oguma, H Ohguro, T Morifuji, E Morimoto, T Momose, HS Kimijima, H Katsumata, Y Iwai, H
Citation: T. Yoshitomi et al., A high performance 0.15 mu m buried channel pMOSFET with extremely shallowcounter doped channel region using solid phase diffusion, SOL ST ELEC, 43(7), 1999, pp. 1209-1214
A study of self-aligned doped channel MOSFET structure for low power and low 1/f noise operation
Authors: Yoshitomi, T Kimijima, H Ishizuka, S Miyahara, Y Ohguro, T Morifuji, E Morimoto, T Momose, HS Katsumata, Y Iwai, H
Citation: T. Yoshitomi et al., A study of self-aligned doped channel MOSFET structure for low power and low 1/f noise operation, SOL ST ELEC, 43(7), 1999, pp. 1219-1224
Single-gate 0.15 and 0.12 mu m CMOS with Co salicide technology
Authors: Yoshitomi, T Saito, M Ohguro, T Ono, M Momose, HS Morifuji, E Morimoto, T Katsumata, Y Iwai, H
Citation: T. Yoshitomi et al., Single-gate 0.15 and 0.12 mu m CMOS with Co salicide technology, SOL ST ELEC, 43(3), 1999, pp. 543-546
An 0.28-mu m CMOS for mixed digital and analog applications with zero-volt-v(th) epitaxial-channel MOSFET's
Authors: Ohguro, T Naruse, H Sugaya, H Morifuji, E Nakamura, S Yoshitomi, T Morimoto, T Kimijima, H Momose, HS Katsumata, Y Iwai, H
Citation: T. Ohguro et al., An 0.28-mu m CMOS for mixed digital and analog applications with zero-volt-v(th) epitaxial-channel MOSFET's, IEEE DEVICE, 46(7), 1999, pp. 1378-1383
Risultati: 1-11 |