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Citation: F. Ducroquet et al., Full CMP integration of CVD TiN damascene sub-0.1-mu m metal gate devices for ULSI applications, IEEE DEVICE, 48(8), 2001, pp. 1816-1821

Authors: Deleonibus, S Caillat, C Guegan, G Heitzmann, M Nier, ME Tedesco, S Dal'zotto, B Martin, F Mur, P Papon, AM Lecarval, G Biswas, S Souil, D

Citation: S. Deleonibus et al., A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF2 pockets, IEEE ELEC D, 21(4), 2000, pp. 173-175

Authors: Deleonibus, S Caillat, C Guegan, G Heitzmann, M Nier, ME Tedesco, SR Dal'zotto, B Martin, F Mur, P Papon, AM Lecarval, G Biswas, S

Citation: S. Deleonibus et al., A 20-nm physical gate length NMOSFET featuring 1.2-nm gate oxide, shallow implanted source and drain and BF2 pockets (vol 21, pg 173, 2000), IEEE ELEC D, 21(12), 2000, pp. 616-616

Authors: Heitzmann, M Nier, ME

Citation: M. Heitzmann et Me. Nier, Process development for 30 nm poly gate patterning on 1.2 nm oxide., MICROEL ENG, 53(1-4), 2000, pp. 159-162

Authors: Palun, L Tedesco, S Heitzman, M Martin, F Fraboulet, D Dal'zotto, B Nier, ME Mur, P Charvolin, T Mariolle, D Tardif, F

Citation: L. Palun et al., Fabrication of single electron devices by hybrid (E-beam/DUV) lithography, MICROEL ENG, 53(1-4), 2000, pp. 167-170