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Results: 1-12 |
Results: 12
NOISE SUPPRESSION SCHEME FOR GIGABIT-SCALE AND GIGABYTE S DATA-RATE LSIS/
Authors: TAKASHIMA D OOWAKI Y WATANABE S OHUCHI K
Citation: D. Takashima et al., NOISE SUPPRESSION SCHEME FOR GIGABIT-SCALE AND GIGABYTE S DATA-RATE LSIS/, IEEE journal of solid-state circuits, 33(2), 1998, pp. 260-267
FOLDED BITLINE ARCHITECTURE FOR A GIGABIT-SCALE NAND DRAM
Authors: SHIRATAKE S TAKASHIMA D HASEGAWA T NAKANO H OOWAKI Y WATANABE S OHSAWA T OHUCHI K
Citation: S. Shiratake et al., FOLDED BITLINE ARCHITECTURE FOR A GIGABIT-SCALE NAND DRAM, IEICE transactions on electronics, E80C(4), 1997, pp. 573-581
AN ULTRA-LOW VOLTAGE SOI CMOS PASS-GATE LOGIC
Authors: FUSE T OOWAKI Y TERAUCHI M WATANABE S YOSHIMI M OHUCHI K MATSUNAGA J
Citation: T. Fuse et al., AN ULTRA-LOW VOLTAGE SOI CMOS PASS-GATE LOGIC, IEICE transactions on electronics, E80C(3), 1997, pp. 472-477
A NOVEL POWER-OFF MODE FOR A BATTERY-BACKUP DRAM
Authors: TAKASHIMA D OOWAKI Y
Citation: D. Takashima et Y. Oowaki, A NOVEL POWER-OFF MODE FOR A BATTERY-BACKUP DRAM, IEEE journal of solid-state circuits, 32(1), 1997, pp. 86-91
A 250 MV BIT-LINE SWING SCHEME FOR 1-V OPERATING GIGABIT SCALE DRAMS
Authors: INABA T TAKASHIMA D OOWAKI Y OZAKI T WATANABE S OHSAWA T OHUCHI K TANGO H
Citation: T. Inaba et al., A 250 MV BIT-LINE SWING SCHEME FOR 1-V OPERATING GIGABIT SCALE DRAMS, IEICE transactions on electronics, E79C(12), 1996, pp. 1699-1706
NEW ALPHA-PARTICLE INDUCED SOFT ERROR MECHANISM IN A 3-DIMENSIONAL CAPACITOR CELL
Authors: OOWAKI Y MABUCHI K WATANABE S OHUCHI K MATSUNAGA J MASUOKA F
Citation: Y. Oowaki et al., NEW ALPHA-PARTICLE INDUCED SOFT ERROR MECHANISM IN A 3-DIMENSIONAL CAPACITOR CELL, IEICE transactions on electronics, E78C(7), 1995, pp. 845-851
A NOVEL CIRCUIT TECHNOLOGY WITH SURROUNDING GATE TRANSISTORS (SGTS) FOR ULTRA-HIGH DENSITY DRAMS
Authors: WATANABE S TSUCHIDA K TAKASHIMA D OOWAKI Y NITAYAMA A HIEDA K TAKATO H SUNOUCHI K HORIGUCHI F OHUCHI K MASUOKA F HARA H
Citation: S. Watanabe et al., A NOVEL CIRCUIT TECHNOLOGY WITH SURROUNDING GATE TRANSISTORS (SGTS) FOR ULTRA-HIGH DENSITY DRAMS, IEEE journal of solid-state circuits, 30(9), 1995, pp. 960-971
STANDBY ACTIVE-MODE LOGIC FOR SUB-1-V OPERATING ULSI MEMORY
Authors: TAKASHIMA D WATANABE S NAKANO H OOWAKI Y OHUCHI K TANGO H
Citation: D. Takashima et al., STANDBY ACTIVE-MODE LOGIC FOR SUB-1-V OPERATING ULSI MEMORY, IEICE transactions on electronics, E77C(5), 1994, pp. 771-777
OPEN FOLDED BIT-LINE ARRANGEMENT FOR ULTRA-HIGH-DENSITY DRAMS
Authors: TAKASHIMA D WATANABE S NAKANO H OOWAKI Y OHUCHI K
Citation: D. Takashima et al., OPEN FOLDED BIT-LINE ARRANGEMENT FOR ULTRA-HIGH-DENSITY DRAMS, IEICE transactions on electronics, E77C(5), 1994, pp. 869-872
STANDBY ACTIVE-MODE LOGIC FOR SUB-1-V OPERATING ULSI MEMORY
Authors: TAKASHIMA D WATANABE S NAKANO H OOWAKI Y OHUCHI K TANGO H
Citation: D. Takashima et al., STANDBY ACTIVE-MODE LOGIC FOR SUB-1-V OPERATING ULSI MEMORY, IEEE journal of solid-state circuits, 29(4), 1994, pp. 441-447
OPEN FOLDED BIT-LINE ARRANGEMENT FOR ULTRA-HIGH-DENSITY DRAMS
Authors: TAKASHIMA D WATANABE S NAKANO H OOWAKI Y OHUCHI K
Citation: D. Takashima et al., OPEN FOLDED BIT-LINE ARRANGEMENT FOR ULTRA-HIGH-DENSITY DRAMS, IEEE journal of solid-state circuits, 29(4), 1994, pp. 539-542
AN EXPERIMENTAL DRAM WITH A NAND-STRUCTURED CELL
Authors: HASEGAWA T TAKASHIMA D OGIWARA R OHTA M SHIRATAKE S HAMAMOTO T YAMADA T AOKI M ISHIBASHI S OOWAKI Y WATANABE S MASUOKA F
Citation: T. Hasegawa et al., AN EXPERIMENTAL DRAM WITH A NAND-STRUCTURED CELL, IEEE journal of solid-state circuits, 28(11), 1993, pp. 1099-1104
Risultati: 1-12 |