AAAAAA

   
Results: 1-13 |
Results: 13
Front side and backside OBIT mappings applied to single event transient testing
Authors: Lewis, D Pouget, V Beauchene, T Lapuyade, H Fouillat, P Touboul, A Beaudoin, F Perdu, P
Citation: D. Lewis et al., Front side and backside OBIT mappings applied to single event transient testing, MICROEL REL, 41(9-10), 2001, pp. 1471-1476
Modeling thermal laser stimulation
Authors: Beaudoin, F Chauffleur, X Fradin, JP Perdu, P Desplats, R Lewis, D
Citation: F. Beaudoin et al., Modeling thermal laser stimulation, MICROEL REL, 41(9-10), 2001, pp. 1477-1482
A new versatile testing interface for failure analysis in integrated circuits
Authors: Desplats, R Perdu, P Beaudoin, F
Citation: R. Desplats et al., A new versatile testing interface for failure analysis in integrated circuits, MICROEL REL, 41(9-10), 2001, pp. 1495-1499
Backside localization of current leakage faults using thermal laser stimulation
Authors: Desplats, R Beaudoin, F Perdu, P Poirier, P Tremouilles, D Bafleur, M Lewis, D
Citation: R. Desplats et al., Backside localization of current leakage faults using thermal laser stimulation, MICROEL REL, 41(9-10), 2001, pp. 1539-1544
Silicon thinning and polishing on packaged devices
Authors: Beaudoin, F Perdu, P Desplats, R Rigo, S Lewis, D
Citation: F. Beaudoin et al., Silicon thinning and polishing on packaged devices, MICROEL REL, 41(9-10), 2001, pp. 1557-1561
Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology
Authors: Bertrand, G Delage, C Bafleur, M Nolhier, N Dorkel, JM Nguyen, Q Mauran, N Tremouilles, D Perdu, P
Citation: G. Bertrand et al., Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology, IEEE J SOLI, 36(9), 2001, pp. 1373-1381
Faster fault isolation using a dichotomy reduction of node candidates
Authors: Desplats, R Rolland, G Perdu, P
Citation: R. Desplats et al., Faster fault isolation using a dichotomy reduction of node candidates, MICROEL REL, 40(8-10), 2000, pp. 1419-1424
New non-destructive laser ablation based backside sample preparation method
Authors: Beaudoin, F Saviot, F Lewis, D Perdu, P Salin, F
Citation: F. Beaudoin et al., New non-destructive laser ablation based backside sample preparation method, MICROEL REL, 40(8-10), 2000, pp. 1425-1429
A review of sample backside preparation techniques for VLSI
Authors: Perdu, P Desplats, R Beaudoin, F
Citation: P. Perdu et al., A review of sample backside preparation techniques for VLSI, MICROEL REL, 40(8-10), 2000, pp. 1431-1436
Calculation of the optimal FIB milling and deposition operations for easier and faster circuit reconfiguration
Authors: Desplats, R Dargnies, T Courrege, JC Perdu, P Noullet, JL
Citation: R. Desplats et al., Calculation of the optimal FIB milling and deposition operations for easier and faster circuit reconfiguration, MICROEL REL, 40(8-10), 2000, pp. 1759-1764
Electron beam testing of FPGA circuits
Authors: Desplats, R Perdu, P Benteo, B Grangy, A
Citation: R. Desplats et al., Electron beam testing of FPGA circuits, MICROEL REL, 39(6-7), 1999, pp. 963-968
FIB voltage contrast measurement for enhanced circuit repairs
Authors: Desplats, R Benteo, B Perdu, P
Citation: R. Desplats et al., FIB voltage contrast measurement for enhanced circuit repairs, MICROEL REL, 39(6-7), 1999, pp. 1003-1008
Defect localization using voltage contrast I-DDQ testing
Authors: Perdu, P Desplats, R
Citation: P. Perdu et R. Desplats, Defect localization using voltage contrast I-DDQ testing, MICROEL REL, 39(6-7), 1999, pp. 1021-1026
Risultati: 1-13 |