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Results: 1-19 |
Results: 19
A COMPARISON OF SELF-ORGANIZING NEURAL NETWORKS FOR FAST CLUSTERING OF RADAR PULSES
Authors: GRANGER E SAVARIA Y LAVOIE P CANTIN MA
Citation: E. Granger et al., A COMPARISON OF SELF-ORGANIZING NEURAL NETWORKS FOR FAST CLUSTERING OF RADAR PULSES, Signal processing, 64(3), 1998, pp. 249-269
PIPELINED H-TREES FOR HIGH-SPEED CLOCKING OF LARGE INTEGRATED SYSTEMSIN PRESENCE OF PROCESS VARIATIONS
Authors: NEKILI M BOIS G SAVARIA Y
Citation: M. Nekili et al., PIPELINED H-TREES FOR HIGH-SPEED CLOCKING OF LARGE INTEGRATED SYSTEMSIN PRESENCE OF PROCESS VARIATIONS, IEEE transactions on very large scale integration (VLSI) systems, 5(2), 1997, pp. 161-174
RATIOED VOTER CIRCUIT FOR TESTING AND FAULT-TOLERANCE IN VLSI PROCESSING ARRAYS
Authors: BELABBES NE GUTERMAN AJ SAVARIA Y DAGENAIS M
Citation: Ne. Belabbes et al., RATIOED VOTER CIRCUIT FOR TESTING AND FAULT-TOLERANCE IN VLSI PROCESSING ARRAYS, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 43(2), 1996, pp. 143-152
DESIGN AND OPTIMIZATION OF A LOW DC OFFSET CMOS CURRENT-SOURCE DEDICATED TO IMPLANTABLE MINIATURIZED STIMULATORS
Authors: STAMAND R SAWAN M SAVARIA Y
Citation: R. Stamand et al., DESIGN AND OPTIMIZATION OF A LOW DC OFFSET CMOS CURRENT-SOURCE DEDICATED TO IMPLANTABLE MINIATURIZED STIMULATORS, Analog integrated circuits and signal processing, 11(1), 1996, pp. 47-61
RECONSTRUCTION METHOD FOR JITTER TOLERANT DATA-ACQUISITION SYSTEM
Authors: BELHAOUANE A SAVARIA Y KAMINSKA B MASSICOTTE D
Citation: A. Belhaouane et al., RECONSTRUCTION METHOD FOR JITTER TOLERANT DATA-ACQUISITION SYSTEM, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 9(1-2), 1996, pp. 177-185
ANALYSIS, ESTIMATION AND REDUCTION OF SIM ULTANEOUS SWITCHING NOISE
Authors: ABDERRAHMAN A SAVARIA Y KAMINSKA B
Citation: A. Abderrahman et al., ANALYSIS, ESTIMATION AND REDUCTION OF SIM ULTANEOUS SWITCHING NOISE, Canadian journal of electrical and computer engineering, 21(4), 1996, pp. 133-143
IEEE VLSI TEST SYMPOSIUM - MEETING THE QUALITY CHALLENGE
Authors: SAVARIA Y THIBEAULT C IVANOV A
Citation: Y. Savaria et al., IEEE VLSI TEST SYMPOSIUM - MEETING THE QUALITY CHALLENGE, IEEE design & test of computers, 13(3), 1996, pp. 110-112
TIMING ANALYSIS SPEED-UP USING A HIERARCHICAL AND A MULTIMODE APPROACH
Authors: BLAQUIERE Y DAGENAIS M SAVARIA Y
Citation: Y. Blaquiere et al., TIMING ANALYSIS SPEED-UP USING A HIERARCHICAL AND A MULTIMODE APPROACH, IEEE transactions on computer-aided design of integrated circuits and systems, 15(2), 1996, pp. 244-255
BOUNDS ON THE PERFORMANCE OF PARTIAL SELECTION NETWORKS
Authors: BELZILE J SAVARIA Y HACCOUN D CHALIFOUX M
Citation: J. Belzile et al., BOUNDS ON THE PERFORMANCE OF PARTIAL SELECTION NETWORKS, IEEE transactions on communications, 43(2-4), 1995, pp. 1800-1809
A NEW EFFICIENT ALGORITHMIC-BASED SEU TOLERANT SYSTEM ARCHITECTURE
Authors: BLAQUIERE T GAGNE G SAVARIA Y EVEQUOZ C
Citation: T. Blaquiere et al., A NEW EFFICIENT ALGORITHMIC-BASED SEU TOLERANT SYSTEM ARCHITECTURE, IEEE transactions on nuclear science, 42(6), 1995, pp. 1599-1606
AN APPLICATION-SPECIFIC PROCESSOR DEDICATED TO KALMAN-FILTER-BASED CORRECTION OF SPECTROMETRIC DATA
Authors: BARWICZ A MASSICOTTE D SAVARIA Y PANGO PA MORAWSKI RZ
Citation: A. Barwicz et al., AN APPLICATION-SPECIFIC PROCESSOR DEDICATED TO KALMAN-FILTER-BASED CORRECTION OF SPECTROMETRIC DATA, IEEE transactions on instrumentation and measurement, 44(3), 1995, pp. 720-724
EQUIVALENCE PROOFS OF SOME YIELD MODELING METHODS FOR DEFECT-TOLERANTINTEGRATED-CIRCUITS
Authors: THIBEAULT C SAVARIA Y HOULE JL
Citation: C. Thibeault et al., EQUIVALENCE PROOFS OF SOME YIELD MODELING METHODS FOR DEFECT-TOLERANTINTEGRATED-CIRCUITS, I.E.E.E. transactions on computers, 44(5), 1995, pp. 724-728
PRODUCING RELIABLE INITIALIZATION AND TEST OF SEQUENTIAL-CIRCUITS WITH PSEUDORANDOM VECTORS
Authors: SOUFI M SAVARIA Y DARLAY F KAMINSKA B
Citation: M. Soufi et al., PRODUCING RELIABLE INITIALIZATION AND TEST OF SEQUENTIAL-CIRCUITS WITH PSEUDORANDOM VECTORS, I.E.E.E. transactions on computers, 44(10), 1995, pp. 1251-1256
AN ARCHITECTURAL APPROACH FOR INCREASING CLOCK FREQUENCY AND COMMUNICATION SPEED IN MONOLITHIC WSI SYSTEMS
Authors: AUDET D SAVARIA Y
Citation: D. Audet et Y. Savaria, AN ARCHITECTURAL APPROACH FOR INCREASING CLOCK FREQUENCY AND COMMUNICATION SPEED IN MONOLITHIC WSI SYSTEMS, IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, 17(3), 1994, pp. 362-368
A MULTIPROCESSOR ARCHITECTURE FOR MULTIPLE PATH STACK SEQUENTIAL DECODERS
Authors: BELANGER N HACCOUN D SAVARIA Y
Citation: N. Belanger et al., A MULTIPROCESSOR ARCHITECTURE FOR MULTIPLE PATH STACK SEQUENTIAL DECODERS, IEEE transactions on communications, 42(2-4), 1994, pp. 951-957
A SYSTOLIC ARCHITECTURE FOR FAST STACK SEQUENTIAL DECODERS
Authors: LAVOIE P HACCOUN D SAVARIA Y
Citation: P. Lavoie et al., A SYSTOLIC ARCHITECTURE FOR FAST STACK SEQUENTIAL DECODERS, IEEE transactions on communications, 42(2-4), 1994, pp. 324-335
AN INTEGRATED STRUCTURE FOR KALMAN-FILTER-BASED MEASURAND RECONSTRUCTION
Authors: BARWICZ A MASSICOTTE D SAVARIA Y SANTERRE MA MORAWSKI RZ
Citation: A. Barwicz et al., AN INTEGRATED STRUCTURE FOR KALMAN-FILTER-BASED MEASURAND RECONSTRUCTION, IEEE transactions on instrumentation and measurement, 43(3), 1994, pp. 403-410
A FAST METHOD TO EVALUATE THE OPTIMUM NUMBER OF SPARES IN DEFECT-TOLERANT INTEGRATED-CIRCUITS
Authors: THIBEAULT C SAVARIA Y HOULE JL
Citation: C. Thibeault et al., A FAST METHOD TO EVALUATE THE OPTIMUM NUMBER OF SPARES IN DEFECT-TOLERANT INTEGRATED-CIRCUITS, I.E.E.E. transactions on computers, 43(6), 1994, pp. 687-697
METHODOLOGY FOR EFFICIENTLY INSERTING AND CONDENSING TEST POINTS
Authors: YOUSSEF M SAVARIA Y KAMINSKA B
Citation: M. Youssef et al., METHODOLOGY FOR EFFICIENTLY INSERTING AND CONDENSING TEST POINTS, IEE proceedings. Part E. Computers and digital techniques, 140(3), 1993, pp. 154-160
Risultati: 1-19 |