Authors:
Nishinohara, KT
Akasaka, Y
Saito, T
Yagishita, A
Murakoshi, A
Suguro, K
Arikado, T
Citation: Kt. Nishinohara et al., Surface channel metal gate complementary MOS with light counter doping andsingle work function gate electrode, JPN J A P 1, 40(4B), 2001, pp. 2603-2606
Authors:
Sugizaki, T
Murakoshi, A
Ozawa, Y
Nakanishi, T
Suguro, K
Citation: T. Sugizaki et al., Dual-thickness gate oxidation technology with halogen/xenon implantation for embedded dynamic random access memories, JPN J A P 1, 40(4B), 2001, pp. 2674-2678
Authors:
Ohuchi, K
Adachi, K
Murakoshi, A
Hokazono, A
Kanemura, T
Aoki, N
Nishigohri, M
Suguro, K
Toyoshima, Y
Citation: K. Ohuchi et al., Ultrashallow junction formation for sub-100 nm complementary metal-oxide-semiconductor field-effect transistor by controlling transient enhanced diffusion, JPN J A P 1, 40(4B), 2001, pp. 2701-2705
Authors:
Inumiya, S
Yagishita, A
Saito, T
Hotta, M
Ozawa, Y
Suguro, K
Tsunashima, Y
Arikado, T
Citation: S. Inumiya et al., Sub-1.3 nm amorphous tantalum pentoxide gate dielectrics for damascene metal gate transistors, JPN J A P 1, 39(4B), 2000, pp. 2087-2093
Authors:
Matsuo, K
Nakajima, K
Omoto, S
Nakamura, S
Yagishita, A
Minamihaba, G
Yano, H
Suguro, K
Citation: K. Matsuo et al., Low leakage TiO2 gate insulator formed by ultrathin TiN deposition and low-temperature oxidation, JPN J A P 1, 39(10), 2000, pp. 5794-5799
Authors:
Saito, T
Yagishita, A
Inumiya, S
Nakajima, K
Akasaka, Y
Ozawa, Y
Yano, H
Hieda, K
Suguro, K
Arikado, T
Okumura, K
Citation: T. Saito et al., Plasma-damage-free gate process using chemical mechanical polishing for 0.1 mu m MOSFETs, JPN J A P 1, 38(4B), 1999, pp. 2227-2231
Authors:
Ohuchi, K
Miyashita, K
Murakoshi, A
Yoshimura, Z
Suguro, K
Toyoshima, Y
Citation: K. Ohuchi et al., Improved Ti self-aligned silicide technology using high dose Ge pre-amorphization for 0.10 mu m CMOS and beyond, JPN J A P 1, 38(4B), 1999, pp. 2238-2242
Authors:
Akasaka, Y
Miyano, K
Nakajima, K
Takahashi, M
Tanaka, S
Suguro, K
Citation: Y. Akasaka et al., Highly uniform low-pressure chemical vapor deposition (LP-CVD) of Si3N4 film on tungsten for advanced low-resistivity "polymetal" gate interconnects, JPN J A P 1, 38(4B), 1999, pp. 2385-2389