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Results: 1-8 |
Results: 8
Precise characterization of long-distance mismatch of CMOS devices
Authors: Schaper, U Linnenbank, CG Thewes, R
Citation: U. Schaper et al., Precise characterization of long-distance mismatch of CMOS devices, IEEE SEMIC, 14(4), 2001, pp. 311-317
Low-frequency noise of integrated poly-silicon resistors
Authors: Brederlow, R Weber, W Dahl, C Schmitt-Landsiedel, D Thewes, R
Citation: R. Brederlow et al., Low-frequency noise of integrated poly-silicon resistors, IEEE DEVICE, 48(6), 2001, pp. 1180-1187
Effect of parameter variations at chip and wafer level on clock skews
Authors: Sauter, S Schmitt-Landsiedel, D Thewes, R Weber, W
Citation: S. Sauter et al., Effect of parameter variations at chip and wafer level on clock skews, IEEE SEMIC, 13(4), 2000, pp. 395-400
Mismatch of MOSFET small signal parameters under analog operation
Authors: Thewes, R Linnenbank, C Kollmer, U Burges, S Schaper, U Brederlow, R Weber, W
Citation: R. Thewes et al., Mismatch of MOSFET small signal parameters under analog operation, IEEE ELEC D, 21(12), 2000, pp. 552-553
MOS transistor reliability under analog operation
Authors: Thewes, R Brederlow, R Schlunder, C Wieczorek, P Ankele, B Hesener, A Holz, J Kessel, S Weber, W
Citation: R. Thewes et al., MOS transistor reliability under analog operation, MICROEL REL, 40(8-10), 2000, pp. 1545-1554
On the design robustness of threshold logic gates using multi-input floating gate MOS transistors
Authors: Luck, A Jung, S Brederlow, R Thewes, R Goser, K Weber, W
Citation: A. Luck et al., On the design robustness of threshold logic gates using multi-input floating gate MOS transistors, IEEE DEVICE, 47(6), 2000, pp. 1231-1240
Trapping mechanisms in negative bias temperature stressed p-MOSFETs
Authors: Schlunder, C Brederlow, R Wieczorek, P Dahl, C Holz, J Rohner, M Kessel, S Herold, V Goser, K Weber, W Thewes, R
Citation: C. Schlunder et al., Trapping mechanisms in negative bias temperature stressed p-MOSFETs, MICROEL REL, 39(6-7), 1999, pp. 821-826
A low-power and high-performance CMOS fingerprint sensing and encoding architecture
Authors: Jung, S Thewes, R Goser, KF Weber, W
Citation: S. Jung et al., A low-power and high-performance CMOS fingerprint sensing and encoding architecture, IEEE J SOLI, 34(7), 1999, pp. 978-984
Risultati: 1-8 |