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Results: 1-10 |
Results: 10
ANALYSIS OF SNUBBER-CLAMPED DIODE-STRING MIXED VOLTAGE INTERFACE ESD PROTECTION NETWORK FOR ADVANCED MICROPROCESSORS (REPRINTED FROM ELECTRICAL OVERSTRESS ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS, 1995)
Authors: VOLDMAN SH GEROSA G GROSS VP DICKSON N FURKAY S SLINKMAN J
Citation: Sh. Voldman et al., ANALYSIS OF SNUBBER-CLAMPED DIODE-STRING MIXED VOLTAGE INTERFACE ESD PROTECTION NETWORK FOR ADVANCED MICROPROCESSORS (REPRINTED FROM ELECTRICAL OVERSTRESS ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS, 1995), Journal of electrostatics, 38(1-2), 1996, pp. 3-31
FAILURE ANALYSIS OF SHALLOW TRENCH-ISOLATED ESD STRUCTURES
Authors: NEVER JM VOLDMAN SH
Citation: Jm. Never et Sh. Voldman, FAILURE ANALYSIS OF SHALLOW TRENCH-ISOLATED ESD STRUCTURES, Journal of electrostatics, 38(1-2), 1996, pp. 93-112
ESD FAILURE MECHANISMS OF INDUCTIVE AND MAGNETORESISTIVE RECORDING-HEADS
Authors: WALLASH AJ HUGHBANKS TS VOLDMAN SH
Citation: Aj. Wallash et al., ESD FAILURE MECHANISMS OF INDUCTIVE AND MAGNETORESISTIVE RECORDING-HEADS, Journal of electrostatics, 38(1-2), 1996, pp. 159-173
MEV IMPLANTS BOOST DEVICE DESIGN
Authors: VOLDMAN SH
Citation: Sh. Voldman, MEV IMPLANTS BOOST DEVICE DESIGN, IEEE circuits and devices magazine, 11(6), 1995, pp. 8-16
ESD PROTECTION IN A MIXED VOLTAGE INTERFACE AND MULTIRAIL DISCONNECTED POWER GRID ENVIRONMENT IN 0.50-MU-M AND 0.25-MU-M CHANNEL-LENGTH CMOS TECHNOLOGIES
Authors: VOLDMAN SH
Citation: Sh. Voldman, ESD PROTECTION IN A MIXED VOLTAGE INTERFACE AND MULTIRAIL DISCONNECTED POWER GRID ENVIRONMENT IN 0.50-MU-M AND 0.25-MU-M CHANNEL-LENGTH CMOS TECHNOLOGIES, IEEE transactions on components, packaging, and manufacturing technology. Part A, 18(2), 1995, pp. 303-313
3-DIMENSIONAL TRANSIENT ELECTROTHERMAL SIMULATION OF ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS
Authors: VOLDMAN SH FURKAY SS SLINKMAN JR
Citation: Sh. Voldman et al., 3-DIMENSIONAL TRANSIENT ELECTROTHERMAL SIMULATION OF ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS, Journal of electrostatics, 36(1), 1995, pp. 55-80
THE EVOLUTION OF IBM CMOS DRAM TECHNOLOGY
Authors: ADLER E DEBROSSE JK GEISSLER SF HOLMES SJ JAFFE MD JOHNSON JB KOBURGER CW LASKY JB LLOYD B MILES GL NAKOS JS NOBLE WP VOLDMAN SH ARMACOST M FERGUSON R
Citation: E. Adler et al., THE EVOLUTION OF IBM CMOS DRAM TECHNOLOGY, IBM journal of research and development, 39(1-2), 1995, pp. 167-188
OVERVIEW OF GATE LINEWIDTH CONTROL IN THE MANUFACTURE OF CMOS LOGIC CHIPS
Authors: CHESEBRO DG ADKISSON JW CLARK LR ESLINGER SN FAUCHER MA HOLMES SJ MALLETTE RP NOWAK EJ SENGLE EW VOLDMAN SH WEEKS TW
Citation: Dg. Chesebro et al., OVERVIEW OF GATE LINEWIDTH CONTROL IN THE MANUFACTURE OF CMOS LOGIC CHIPS, IBM journal of research and development, 39(1-2), 1995, pp. 189-200
SCALING, OPTIMIZATION AND DESIGN CONSIDERATIONS OF ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS IN CMOS TECHNOLOGY
Authors: VOLDMAN SH GROSS VP
Citation: Sh. Voldman et Vp. Gross, SCALING, OPTIMIZATION AND DESIGN CONSIDERATIONS OF ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS IN CMOS TECHNOLOGY, Journal of electrostatics, 33(3), 1994, pp. 327-356
SHALLOW TRENCH ISOLATION DOUBLE-DIODE ELECTROSTATIC DISCHARGE CIRCUITAND INTERACTION WITH DRAM OUTPUT CIRCUITRY
Authors: VOLDMAN SH GROSS VP HARGROVE MJ NEVER JM SLINKMAN JA OBOYLE MP SCOTT TS DELECKI JJ
Citation: Sh. Voldman et al., SHALLOW TRENCH ISOLATION DOUBLE-DIODE ELECTROSTATIC DISCHARGE CIRCUITAND INTERACTION WITH DRAM OUTPUT CIRCUITRY, Journal of electrostatics, 31(2-3), 1993, pp. 237-262
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