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Results: 51-75/3259
Authors:
Shelton, BS
Zhu, TG
Lambert, DJH
Dupuis, RD
Citation: Bs. Shelton et al., Simulation of the electrical characteristics of high-voltage mesa and planar GaN Schottky and p-i-n rectifiers, IEEE DEVICE, 48(8), 2001, pp. 1498-1502
Authors:
Bito, Y
Kato, T
Iwata, N
Citation: Y. Bito et al., Enhancement-mode power heterojunction FET utilizing Al0.5Ga0.5As barrier layer with negligible operation gate current for digital cellular phones, IEEE DEVICE, 48(8), 2001, pp. 1503-1509
Authors:
Makioka, S
Anda, Y
Miyatsuji, K
Ueda, D
Citation: S. Makioka et al., Super self-aligned GaAs RF switch IC with 0.25 dB extremely low insertion loss for mobile communication systems, IEEE DEVICE, 48(8), 2001, pp. 1510-1514
Enhancement of breakdown voltage in AlGaN/GaN high electron mobility transistors using a field plate
Authors:
Karmalkar, S
Mishra, UK
Citation: S. Karmalkar et Uk. Mishra, Enhancement of breakdown voltage in AlGaN/GaN high electron mobility transistors using a field plate, IEEE DEVICE, 48(8), 2001, pp. 1515-1521
Authors:
Liu, WC
Yu, KH
Lin, KW
Tsai, JH
Wu, CZ
Lin, KP
Yen, CH
Citation: Wc. Liu et al., On the InGaP/GaAs/InGaAs camel-like FET for high-breakdown, low-leakage, and high-temperature operations, IEEE DEVICE, 48(8), 2001, pp. 1522-1530
Authors:
Twynam, JK
Yagura, M
Takahashi, N
Suematsu, E
Sakuno, K
Sato, H
Citation: Jk. Twynam et al., Design and analysis of heterojunction bipolar transferred electron devices, IEEE DEVICE, 48(8), 2001, pp. 1531-1539
Authors:
Kwok, KH
Selvakumar, CR
Citation: Kh. Kwok et Cr. Selvakumar, Profile design considerations for minimizing base transit time in SiGeHBTsfor all levels of injection before onset of Kirk effect, IEEE DEVICE, 48(8), 2001, pp. 1540-1549
Authors:
Sekine, K
Saito, Y
Hirayama, M
Ohmi, T
Citation: K. Sekine et al., Highly reliable ultrathin silicon oxide film formation at low temperature by oxygen radical generated in high-density krypton plasma, IEEE DEVICE, 48(8), 2001, pp. 1550-1555
Authors:
Kim, JK
Yang, JH
Chung, WJ
Whang, KW
Citation: Jk. Kim et al., The addressing characteristics of an alternating current plasma display panel adopting a ramping reset pulse, IEEE DEVICE, 48(8), 2001, pp. 1556-1563
Authors:
Liu, SD
Lee, SC
Chern, MY
Citation: Sd. Liu et al., Hydrogenated amorphous silicon-germanium pin x-ray detector, IEEE DEVICE, 48(8), 2001, pp. 1564-1567
Authors:
Motoyama, Y
Matsuzaki, H
Murakami, H
Citation: Y. Motoyama et al., A study of the secondary electron yield gamma of insulator cathodes for plasma display panels, IEEE DEVICE, 48(8), 2001, pp. 1568-1574
Authors:
Gogoi, BP
Wang, CC
Mastrangelo, CH
Citation: Bp. Gogoi et al., Force balanced micromachined pressure sensors, IEEE DEVICE, 48(8), 2001, pp. 1575-1584
Authors:
Gummel, HK
Singhal, K
Citation: Hk. Gummel et K. Singhal, Inversion charge modeling, IEEE DEVICE, 48(8), 2001, pp. 1585-1593
Authors:
Huang, R
Wang, JY
Zhang, X
Wang, YY
Citation: R. Huang et al., Hot carrier induced degradation in mesa-isolated n-channel SOI MOSFETs operating in a Bi-MOS mode, IEEE DEVICE, 48(8), 2001, pp. 1594-1598
Authors:
Endoh, T
Suzuki, M
Sakuraba, H
Masuoka, F
Citation: T. Endoh et al., 2.4F(2) memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM, IEEE DEVICE, 48(8), 2001, pp. 1599-1603
Authors:
Yagishita, A
Saito, T
Nakajima, K
Inumiya, S
Matsuo, K
Shibata, T
Tsunashima, Y
Suguro, K
Arikado, T
Citation: A. Yagishita et al., Improvement of threshold voltage deviation in damascene metal gate transistors, IEEE DEVICE, 48(8), 2001, pp. 1604-1611
Authors:
Mizuno, T
Sugiyama, N
Kurobe, A
Takagi, S
Citation: T. Mizuno et al., Advanced SOI p-MOSFETs with strained-Si channel on SiGe-on-insulator substrate fabricated by SIMOX technology, IEEE DEVICE, 48(8), 2001, pp. 1612-1618
Authors:
Shimada, H
Ohshima, I
Ushiki, T
Sugawa, S
Ohmi, T
Citation: H. Shimada et al., Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivity self-grown bcc-tantalum layer, IEEE DEVICE, 48(8), 2001, pp. 1619-1626
Authors:
Huang, HJ
Chen, KM
Huang, TY
Chao, TS
Huang, GW
Chien, CH
Chang, CY
Citation: Hj. Huang et al., Improved low temperature characteristics of p-channel MOSFETs with Si1-xGex raised source and drain, IEEE DEVICE, 48(8), 2001, pp. 1627-1632
Authors:
Takamiya, M
Hiramoto, T
Citation: M. Takamiya et T. Hiramoto, High drive-current electrically induced body dynamic threshold SOI MOSFET (EIB-DTMOS) with large body effect and low threshold voltage, IEEE DEVICE, 48(8), 2001, pp. 1633-1640
Authors:
Versari, R
Esseni, D
Falavigna, G
Lanzoni, M
Ricco, B
Citation: R. Versari et al., Optimized programming of multilevel flash EEPROMs, IEEE DEVICE, 48(8), 2001, pp. 1641-1646
Authors:
Porret, AS
Sallese, JM
Enz, CC
Citation: As. Porret et al., A compact non-quasi-static extension of a charge-based MOS model, IEEE DEVICE, 48(8), 2001, pp. 1647-1654
Authors:
Wang, MX
Wong, M
Citation: Mx. Wang et M. Wong, Characterization of an individual grain boundary in metal-induced laterally crystallized polycrystalline silicon thin-film devices, IEEE DEVICE, 48(8), 2001, pp. 1655-1660
Authors:
Drobny, VF
Rubalcava, J
Citation: Vf. Drobny et J. Rubalcava, Doping characteristics of BF2+ implants in < 100 > and < 111 > silicon, IEEE DEVICE, 48(8), 2001, pp. 1661-1666
Authors:
Gleskova, H
Wagner, S
Citation: H. Gleskova et S. Wagner, DC-gate-bias stressing of a-Si : H TFTs fabricated at 150 degrees C on polyimide foil, IEEE DEVICE, 48(8), 2001, pp. 1667-1671