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Results: 26-50/123
Authors:
PAPADOPOULOS CV
Citation: Cv. Papadopoulos, ON THE ROUTING OF SIGNALS IN PARALLEL PROCESSOR MESHES (VOL 41, PG 171, 1995), Microprocessing and microprogramming, 41(5-6), 1995, pp. 2-2
Authors:
CATTHOOR F
MOONEN M
Citation: F. Catthoor et M. Moonen, PARALLEL PROGRAMMABLE ARCHITECTURES AND COMPILATION FOR MULTIDIMENSIONAL PROCESSING, Microprocessing and microprogramming, 41(5-6), 1995, pp. 333-337
Authors:
KONIG J
THIELE L
Citation: J. Konig et L. Thiele, ALGORITHM-ARCHITECTURE CO-DESIGN BY EXAMPLE - A COPROCESSOR FOR ONLINE ARITHMETIC, Microprocessing and microprogramming, 41(5-6), 1995, pp. 339-357
Authors:
DUBOUX T
FERREIRA A
GASTALDO M
Citation: T. Duboux et al., A SCALABLE DESIGN FOR VLSI DICTIONARY MACHINES, Microprocessing and microprogramming, 41(5-6), 1995, pp. 359-372
Authors:
VISSERS KA
ESSINK G
VANGERWEN PHJ
JANSSEN PJM
POPP O
RIDDERSMA E
SMITS WJM
VEENDRICK HJM
Citation: Ka. Vissers et al., ARCHITECTURE AND PROGRAMMING OF 2 GENERATIONS VIDEO SIGNAL PROCESSORS, Microprocessing and microprogramming, 41(5-6), 1995, pp. 373-390
Authors:
KNEIP J
OHMACHT M
RONNER K
PIRSCH P
Citation: J. Kneip et al., ARCHITECTURE AND C-PROGRAMMING ENVIRONMENT OF A HIGHLY PARALLEL IMAGESIGNAL PROCESSOR(+), Microprocessing and microprogramming, 41(5-6), 1995, pp. 391-408
Authors:
DEGREEF E
CATTHOOR F
DEMAN H
Citation: E. Degreef et al., MAPPING REAL-TIME MOTION ESTIMATION TYPE ALGORITHMS TO MEMORY EFFICIENT, PROGRAMMABLE MULTIPROCESSOR ARCHITECTURES, Microprocessing and microprogramming, 41(5-6), 1995, pp. 409-423
Authors:
FEAUTRIER P
Citation: P. Feautrier, COMPILING FOR MASSIVELY-PARALLEL ARCHITECTURES - A PERSPECTIVE, Microprocessing and microprogramming, 41(5-6), 1995, pp. 425-439
Authors:
POSCH R
PUCHER F
Citation: R. Posch et F. Pucher, AN EXPERIMENTAL MIXED PURPOSE NETWORK, Microprocessing and microprogramming, 41(4), 1995, pp. 263-271
Authors:
BASU SK
GUPTA JD
GUPTA RD
Citation: Sk. Basu et al., ON SYNTHESIZING CUBE AND TREE FOR PARALLEL-PROCESSING, Microprocessing and microprogramming, 41(4), 1995, pp. 273-288
Authors:
SONG Q
TEOH EK
MITAL DP
Citation: Q. Song et al., MULTILAYERED NEURAL-NETWORK IMPLEMENTATION ON TRANSPUTER SYSTOLIC ARRAY, Microprocessing and microprogramming, 41(4), 1995, pp. 289-299
Authors:
MAYERLINDENBERG F
Citation: F. Mayerlindenberg, A PARALLEL COMPUTER-BASED ON SIMPLE DSP MODULES, Microprocessing and microprogramming, 41(4), 1995, pp. 301-314
Authors:
LIN JM
TSAI SR
Citation: Jm. Lin et Sr. Tsai, SUPPORTING USER MOBILITY IN THE DISTRIBUTED LOGICAL MACHINE SYSTEM, Microprocessing and microprogramming, 41(4), 1995, pp. 315-330
Authors:
PARTHASARATHI R
JHUNJHUNWALA A
Citation: R. Parthasarathi et A. Jhunjhunwala, MODIFIED STRAIGHT DIVISION - A COMPUTER IMPLEMENTATION OF MULTIPLE-PRECISION DIVISION, Microprocessing and microprogramming, 41(3), 1995, pp. 193-209
Authors:
CHU WL
VASSILIADIS S
DELGADOFRIAS JG
Citation: Wl. Chu et al., THE MULTI-ASSOCIATIVE BRANCH TARGET BUFFER - A COST-EFFECTIVE BTB MECHANISM, Microprocessing and microprogramming, 41(3), 1995, pp. 211-225
Authors:
KWAK JC
MOON S
Citation: Jc. Kwak et S. Moon, 2-DIMENSIONAL SPECIFICATION OF QUERIES IN OBJECT-ORIENTED DATABASES, Microprocessing and microprogramming, 41(3), 1995, pp. 227-244
Authors:
JOSHI RK
RAM DJ
Citation: Rk. Joshi et Dj. Ram, PARSET - A LANGUAGE CONSTRUCT FOR SYSTEM INDEPENDENT PARALLEL PROGRAMMING ON DISTRIBUTED SYSTEMS, Microprocessing and microprogramming, 41(3), 1995, pp. 245-259
Authors:
VAUGHAN JG
Citation: Jg. Vaughan, INCORPORATING JOB SIZES IN DISTRIBUTED LOAD BALANCING, Microprocessing and microprogramming, 41(2), 1995, pp. 111-119
Authors:
PARK JS
AHN GS
Citation: Js. Park et Gs. Ahn, A SOFTWARE-CONTROLLED PREFETCHING MECHANISM FOR SOFTWARE-MANAGED TLBS, Microprocessing and microprogramming, 41(2), 1995, pp. 121-136
Authors:
RAVIKUMAR CP
VEDI N
Citation: Cp. Ravikumar et N. Vedi, HEURISTIC AND NEURAL ALGORITHMS FOR MAPPING TASKS TO A RECONFIGURABLEARRAY, Microprocessing and microprogramming, 41(2), 1995, pp. 137-151
Authors:
VERGOS HT
NIKOLOS D
Citation: Ht. Vergos et D. Nikolos, EFFICIENT FAULT-TOLERANT CACHE MEMORY DESIGN, Microprocessing and microprogramming, 41(2), 1995, pp. 153-169
Authors:
PAPADOPOULOS CV
Citation: Cv. Papadopoulos, ON THE ROUTING OF SIGNALS IN PARALLEL PROCESSOR MESHES, Microprocessing and microprogramming, 41(2), 1995, pp. 171-189
Authors:
SAMI M
RICHTER L
Citation: M. Sami et L. Richter, UNTITLED, Microprocessing and microprogramming, 41(1), 1995, pp. 1-2
Authors:
NG KW
LUK CK
Citation: Kw. Ng et Ck. Luk, A SURVEY OF LANGUAGES INTEGRATING FUNCTIONAL, OBJECT-ORIENTED AND LOGIC PROGRAMMING, Microprocessing and microprogramming, 41(1), 1995, pp. 5-36
Authors:
HUANG SH
HWANG CT
HSU YC
OYANG YJ
Citation: Sh. Huang et al., A NEW APPROACH TO SCHEDULE OPERATIONS ACROSS NESTED-IFS AND NESTED-LOOPS, Microprocessing and microprogramming, 41(1), 1995, pp. 37-52