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Results: 1-19 |
Results: 19
Untitled
Authors: Agrawal, VD
Citation: Vd. Agrawal, Untitled, J ELEC TEST, 17(5), 2001, pp. 367-367
Untitled
Authors: Agrawal, VD
Citation: Vd. Agrawal, Untitled, J ELEC TEST, 17(3-4), 2001, pp. 203-203
Untitled
Authors: Agrawal, VD
Citation: Vd. Agrawal, Untitled, J ELEC TEST, 17(2), 2001, pp. 79-79
Improving path delay testability of sequential circuits
Authors: Chakraborty, TJ Agrawal, VD Bushnell, ML
Citation: Tj. Chakraborty et al., Improving path delay testability of sequential circuits, IEEE VLSI, 8(6), 2000, pp. 736-741
Line coverage of path delay faults
Authors: Majhi, AK Agrawal, VD Jacob, J Patnaik, LM
Citation: Ak. Majhi et al., Line coverage of path delay faults, IEEE VLSI, 8(5), 2000, pp. 610-614
Path delay fault simulation of sequential circuits
Authors: Chakraborty, TJ Agrawal, VD Bushnell, ML
Citation: Tj. Chakraborty et al., Path delay fault simulation of sequential circuits, IEEE VLSI, 8(2), 2000, pp. 223-228
Untitled
Authors: Agrawal, VD
Citation: Vd. Agrawal, Untitled, J ELEC TEST, 16(6), 2000, pp. 571-571
Untitled
Authors: Agrawal, VD
Citation: Vd. Agrawal, Untitled, J ELEC TEST, 16(5), 2000, pp. 403-404
False-path removal using delay fault simulation
Authors: Gharaybeh, MA Agrawal, VD Bushnell, ML Parodi, CG
Citation: Ma. Gharaybeh et al., False-path removal using delay fault simulation, J ELEC TEST, 16(5), 2000, pp. 463-476
Special issue on the European Test Workshop 1999
Authors: Agrawal, VD
Citation: Vd. Agrawal, Special issue on the European Test Workshop 1999, J ELEC TEST, 16(3), 2000, pp. 163-163
Editorial
Authors: Agrawal, VD
Citation: Vd. Agrawal, Editorial, J ELEC TEST, 16(1-2), 2000, pp. 5-5
Untitled
Authors: Agrawal, VD
Citation: Vd. Agrawal, Untitled, J ELEC TEST, 15(3), 1999, pp. 215-215
Editorial
Authors: Agrawal, VD
Citation: Vd. Agrawal, Editorial, J ELEC TEST, 15(1-2), 1999, pp. 5-5
Untitled
Authors: Agrawal, VD
Citation: Vd. Agrawal, Untitled, J ELEC TEST, 14(3), 1999, pp. 187-188
Untitled
Authors: Agrawal, VD
Citation: Vd. Agrawal, Untitled, J ELEC TEST, 14(1-2), 1999, pp. 7-7
Untitled
Authors: Agrawal, VD
Citation: Vd. Agrawal, Untitled, J ELEC TEST, 13(3), 1998, pp. 219-219
Special issue on high-level test synthesis
Authors: Agrawal, VD
Citation: Vd. Agrawal, Special issue on high-level test synthesis, J ELEC TEST, 13(2), 1998, pp. 75-75
Untitled
Authors: Agrawal, VD
Citation: Vd. Agrawal, Untitled, J ELEC TEST, 13(1), 1998, pp. 5-5
Design of mixed-signal systems for testability
Authors: Agrawal, VD
Citation: Vd. Agrawal, Design of mixed-signal systems for testability, INTEGRATION, 26(1-2), 1998, pp. 141-150
Risultati: 1-19 |