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Shreedhara, JK
Barnaby, HJ
Bhuva, BL
Kerns, DV
Kerns, SE
Citation: Jk. Shreedhara et al., Circuit technique for threshold voltage stabilization using substrate biasin total dose environments, IEEE NUCL S, 47(6), 2000, pp. 2557-2560
Authors:
Barnaby, HJ
Cirba, C
Schrimpf, RD
Kosier, SL
Fouillat, P
Montagner, X
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Citation: Xw. Zhu et al., Charge deposition modeling of thermal neutron products in fast submicron MOS devices, IEEE NUCL S, 46(6), 1999, pp. 1378-1385
Authors:
Barnaby, HJ
Cirba, C
Schrimpf, RD
Kosier, S
Fouillat, P
Montagner, X
Citation: Hj. Barnaby et al., Minimizing gain degradation in lateral PNP bipolar junction transistors using gate control, IEEE NUCL S, 46(6), 1999, pp. 1652-1659
Authors:
Barnaby, HJ
Schrimpf, RD
Pease, RL
Cole, P
Turflinger, T
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Emily, D
Gehlhausen, M
Witczak, SC
Maher, MC
Van Nort, D
Citation: Hj. Barnaby et al., Identification of degradation mechanisms in a bipolar linear voltage comparator through correlation of transistor and circuit response, IEEE NUCL S, 46(6), 1999, pp. 1666-1673
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