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Results: 1-12 |
Results: 12
REDUNDANCY REMOVAL AND TEST-GENERATION FOR CIRCUITS WITH NON-BOOLEAN PRIMITIVES
Authors: CHAKRADHAR ST ROTHWEILER SG AGRAWAL VD
Citation: St. Chakradhar et al., REDUNDANCY REMOVAL AND TEST-GENERATION FOR CIRCUITS WITH NON-BOOLEAN PRIMITIVES, IEEE transactions on computer-aided design of integrated circuits and systems, 16(11), 1997, pp. 1370-1377
BOTTLENECK REMOVAL ALGORITHM FOR DYNAMIC COMPACTION IN SEQUENTIAL-CIRCUITS
Authors: CHAKRADHAR ST RAGHUNATHAN A
Citation: St. Chakradhar et A. Raghunathan, BOTTLENECK REMOVAL ALGORITHM FOR DYNAMIC COMPACTION IN SEQUENTIAL-CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 16(10), 1997, pp. 1157-1172
SYNTHESIS OF INITIALIZABLE ASYNCHRONOUS CIRCUITS
Authors: CHAKRADHAR ST BANERJEE S ROY RK PRADHAN DK
Citation: St. Chakradhar et al., SYNTHESIS OF INITIALIZABLE ASYNCHRONOUS CIRCUITS, IEEE transactions on very large scale integration (VLSI) systems, 4(2), 1996, pp. 254-263
INITIALIZATION ISSUES IN ASYNCHRONOUS CIRCUIT SYNTHESIS
Authors: BANERJEE S ROY RK CHAKRADHAR ST
Citation: S. Banerjee et al., INITIALIZATION ISSUES IN ASYNCHRONOUS CIRCUIT SYNTHESIS, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 9(3), 1996, pp. 237-250
AN EXACT ALGORITHM FOR SELECTING PARTIAL SCAN FLIP-FLOPS
Authors: CHAKRADHAR ST BALAKRISHNAN A AGRAWAL V
Citation: St. Chakradhar et al., AN EXACT ALGORITHM FOR SELECTING PARTIAL SCAN FLIP-FLOPS, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 7(1-2), 1995, pp. 83-93
DESIGN OF TESTABLE SEQUENTIAL-CIRCUITS BY REPOSITIONING FLIP-FLOPS
Authors: DEY S CHAKRADHAR ST
Citation: S. Dey et St. Chakradhar, DESIGN OF TESTABLE SEQUENTIAL-CIRCUITS BY REPOSITIONING FLIP-FLOPS, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 7(1-2), 1995, pp. 105-114
TEST FUNCTION EMBEDDING ALGORITHMS WITH APPLICATION TO INTERCONNECTEDFINITE-STATE MACHINES
Authors: KANJILAL S CHAKRADHAR ST AGRAWAL VD
Citation: S. Kanjilal et al., TEST FUNCTION EMBEDDING ALGORITHMS WITH APPLICATION TO INTERCONNECTEDFINITE-STATE MACHINES, IEEE transactions on computer-aided design of integrated circuits and systems, 14(9), 1995, pp. 1115-1127
COMBINATIONAL ATPG THEOREMS FOR IDENTIFYING UNTESTABLE FAULTS IN SEQUENTIAL-CIRCUITS
Authors: AGRAWAL VD CHAKRADHAR ST
Citation: Vd. Agrawal et St. Chakradhar, COMBINATIONAL ATPG THEOREMS FOR IDENTIFYING UNTESTABLE FAULTS IN SEQUENTIAL-CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(9), 1995, pp. 1155-1160
ENERGY MODELS FOR DELAY TESTING
Authors: CHAKRADHAR ST IYER MA AGRAWAL VD
Citation: St. Chakradhar et al., ENERGY MODELS FOR DELAY TESTING, IEEE transactions on computer-aided design of integrated circuits and systems, 14(6), 1995, pp. 728-739
A PARTITION AND RESYNTHESIS APPROACH TO TESTABLE DESIGN OF LARGE CIRCUITS
Authors: KANJILAL S CHAKRADHAR ST AGRAWAL VD
Citation: S. Kanjilal et al., A PARTITION AND RESYNTHESIS APPROACH TO TESTABLE DESIGN OF LARGE CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(10), 1995, pp. 1268-1276
1ST-ORDER VERSUS 2ND-ORDER SINGLE-LAYER RECURRENT NEURAL NETWORKS
Authors: GOUDREAU MW GILES CL CHAKRADHAR ST CHEN D
Citation: Mw. Goudreau et al., 1ST-ORDER VERSUS 2ND-ORDER SINGLE-LAYER RECURRENT NEURAL NETWORKS, IEEE transactions on neural networks, 5(3), 1994, pp. 511-513
A TRANSITIVE CLOSURE ALGORITHM FOR TEST-GENERATION
Authors: CHAKRADHAR ST AGRAWAL VD ROTHWEILER SG
Citation: St. Chakradhar et al., A TRANSITIVE CLOSURE ALGORITHM FOR TEST-GENERATION, IEEE transactions on computer-aided design of integrated circuits and systems, 12(7), 1993, pp. 1015-1028
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