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Results: 1-25 | 26-27
Results: 1-25/27
POWER ESTIMATION UNDER USER-SPECIFIED INPUT SEQUENCES AND PROGRAMS
Authors: MONTEIRO J DEVADAS S
Citation: J. Monteiro et S. Devadas, POWER ESTIMATION UNDER USER-SPECIFIED INPUT SEQUENCES AND PROGRAMS, Integrated computer-aided engineering, 5(2), 1998, pp. 177-185
A LOW-POWER, LOW BANDWIDTH PROTOCOL FOR REMOTE WIRELESS TERMINALS
Authors: HADJIYIANNIS G CHANDRAKASAN A DEVADAS S
Citation: G. Hadjiyiannis et al., A LOW-POWER, LOW BANDWIDTH PROTOCOL FOR REMOTE WIRELESS TERMINALS, WIRELESS NETWORKS, 4(1), 1998, pp. 3-15
CODE OPTIMIZATION TECHNIQUES IN EMBEDDED DSP MICROPROCESSORS
Authors: LIAO S DEVADAS S KEUTZER K TJIANG S WANG A
Citation: S. Liao et al., CODE OPTIMIZATION TECHNIQUES IN EMBEDDED DSP MICROPROCESSORS, DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, 3(1), 1998, pp. 59-73
BDD-BASED SYNTHESIS OF EXTENDED BURST-MODE CONTROLLERS
Authors: YUN KY LIN B DILL DL DEVADAS S
Citation: Ky. Yun et al., BDD-BASED SYNTHESIS OF EXTENDED BURST-MODE CONTROLLERS, IEEE transactions on computer-aided design of integrated circuits and systems, 17(9), 1998, pp. 782-792
CODE DENSITY OPTIMIZATION FOR EMBEDDED DSP PROCESSORS USING DATA-COMPRESSION TECHNIQUES
Authors: LIAO SY DEVADAS S KEUTZER K
Citation: Sy. Liao et al., CODE DENSITY OPTIMIZATION FOR EMBEDDED DSP PROCESSORS USING DATA-COMPRESSION TECHNIQUES, IEEE transactions on computer-aided design of integrated circuits and systems, 17(7), 1998, pp. 601-608
SEQUENTIAL LOGIC OPTIMIZATION FOR LOW-POWER USING INPUT-DISABLING PRECOMPUTATION ARCHITECTURES
Authors: MONTEIRO J DEVADAS S GHOSH A
Citation: J. Monteiro et al., SEQUENTIAL LOGIC OPTIMIZATION FOR LOW-POWER USING INPUT-DISABLING PRECOMPUTATION ARCHITECTURES, IEEE transactions on computer-aided design of integrated circuits and systems, 17(3), 1998, pp. 279-284
PRELIMINARY STUDIES ON THE EFFECT OF AN ELECTROMAGNETIC-FIELD IN ADJUVANT-INDUCED ARTHRITIS IN RATS
Authors: POORNAPRIYA T MEERA R DEVADAS S PUVANAKRISHNAN R
Citation: T. Poornapriya et al., PRELIMINARY STUDIES ON THE EFFECT OF AN ELECTROMAGNETIC-FIELD IN ADJUVANT-INDUCED ARTHRITIS IN RATS, Medical science research, 26(7), 1998, pp. 467-469
SIGNAL-TRANSDUCTION THERAPY - A KINASE POINT-OF-VIEW
Authors: DEVADAS S PUVANAKRISHNAN R
Citation: S. Devadas et R. Puvanakrishnan, SIGNAL-TRANSDUCTION THERAPY - A KINASE POINT-OF-VIEW, The FASEB journal, 11(9), 1997, pp. 780-780
ESTIMATION OF AVERAGE SWITCHING ACTIVITY IN COMBINATIONAL LOGIC-CIRCUITS USING SYMBOLIC SIMULATION
Authors: MONTEIRO J DEVADAS S GHOSH A KEUTZER K WHITE J
Citation: J. Monteiro et al., ESTIMATION OF AVERAGE SWITCHING ACTIVITY IN COMBINATIONAL LOGIC-CIRCUITS USING SYMBOLIC SIMULATION, IEEE transactions on computer-aided design of integrated circuits and systems, 16(1), 1997, pp. 121-127
TECHNIQUES FOR POWER ESTIMATION AND OPTIMIZATION AT THE LOGIC LEVEL -A SURVEY
Authors: MONTEIRO J DEVADAS S
Citation: J. Monteiro et S. Devadas, TECHNIQUES FOR POWER ESTIMATION AND OPTIMIZATION AT THE LOGIC LEVEL -A SURVEY, Journal of VLSI signal processing systems for signal, image, and video technology, 13(2-3), 1996, pp. 259-276
POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC-CIRCUITS (VOL 3, PG 404, 1995)
Authors: TSUI CY MONTEIRO J PEDRAM M DEVADAS S DESPAIN AM LIN B
Citation: Cy. Tsui et al., POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC-CIRCUITS (VOL 3, PG 404, 1995), IEEE transactions on very large scale integration (VLSI) systems, 4(4), 1996, pp. 495-495
SYNTHESIS OF ROBUST DELAY-FAULT TESTABLE CIRCUITS - THEORY
Authors: DEVADAS S KEUTZER K
Citation: S. Devadas et K. Keutzer, SYNTHESIS OF ROBUST DELAY-FAULT TESTABLE CIRCUITS - THEORY, IEEE transactions on computer-aided design of integrated circuits and systems, 15(4), 1996, pp. 445-446
STORAGE ASSIGNMENT TO DECREASE CODE SIZE
Authors: LIAO S DEVADAS S KEUTZER K TJIANG S WANG A
Citation: S. Liao et al., STORAGE ASSIGNMENT TO DECREASE CODE SIZE, ACM transactions on programming languages and systems, 18(3), 1996, pp. 235-253
STORAGE ASSIGNMENT TO DECREASE CODE SIZE
Authors: LIAO S DEVADAS S KEUTZER K TJIANG S WANG A
Citation: S. Liao et al., STORAGE ASSIGNMENT TO DECREASE CODE SIZE, ACM SIGPLAN NOTICES, 30(6), 1995, pp. 186-195
POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC-CIRCUITS
Authors: TSUI CY MONTEIRO J PEDRAM M DEVADAS S DESPAIN AM LIN B
Citation: Cy. Tsui et al., POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC-CIRCUITS, IEEE transactions on very large scale integration (VLSI) systems, 3(3), 1995, pp. 404-416
SYNTHESIS OF HAZARD-FREE MULTILEVEL LOGIC UNDER MULTIPLE-INPUT CHANGES FROM BINARY DECISION DIAGRAMS
Authors: LIN B DEVADAS S
Citation: B. Lin et S. Devadas, SYNTHESIS OF HAZARD-FREE MULTILEVEL LOGIC UNDER MULTIPLE-INPUT CHANGES FROM BINARY DECISION DIAGRAMS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(8), 1995, pp. 974-985
PROBABILISTIC MANIPULATION OF BOOLEAN FUNCTIONS USING FREE BOOLEAN DIAGRAMS
Authors: SHEN A DEVADAS S GHOSH A
Citation: A. Shen et al., PROBABILISTIC MANIPULATION OF BOOLEAN FUNCTIONS USING FREE BOOLEAN DIAGRAMS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(1), 1995, pp. 87-95
EVENT SUPPRESSION - IMPROVING THE EFFICIENCY OF TIMING SIMULATION FORSYNCHRONOUS DIGITAL CIRCUITS
Authors: DEVADAS S KEUTZER K MALIK S WANG A
Citation: S. Devadas et al., EVENT SUPPRESSION - IMPROVING THE EFFICIENCY OF TIMING SIMULATION FORSYNCHRONOUS DIGITAL CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 13(6), 1994, pp. 814-822
EVENT-BASED VERIFICATION OF SYNCHRONOUS, GLOBALLY CONTROLLED, LOGIC DESIGNS AGAINST SIGNAL FLOW-GRAPHS
Authors: VANAELTEN FV ALLEN J DEVADAS S
Citation: Fv. Vanaelten et al., EVENT-BASED VERIFICATION OF SYNCHRONOUS, GLOBALLY CONTROLLED, LOGIC DESIGNS AGAINST SIGNAL FLOW-GRAPHS, IEEE transactions on computer-aided design of integrated circuits and systems, 13(1), 1994, pp. 122-134
AUTOMATIC-GENERATION AND VERIFICATION OF SUFFICIENT CORRECTNESS PROPERTIES OF SYNCHRONOUS ARRAY PROCESSORS
Authors: LIAO SY DEVADAS S
Citation: Sy. Liao et S. Devadas, AUTOMATIC-GENERATION AND VERIFICATION OF SUFFICIENT CORRECTNESS PROPERTIES OF SYNCHRONOUS ARRAY PROCESSORS, IEICE transactions on information and systems, E76D(9), 1993, pp. 1030-1038
DELAY-FAULT TEST-GENERATION AND SYNTHESIS FOR TESTABILITY UNDER A STANDARD SCAN DESIGN METHODOLOGY
Authors: CHENG KT DEVADAS S KEUTZER K
Citation: Kt. Cheng et al., DELAY-FAULT TEST-GENERATION AND SYNTHESIS FOR TESTABILITY UNDER A STANDARD SCAN DESIGN METHODOLOGY, IEEE transactions on computer-aided design of integrated circuits and systems, 12(8), 1993, pp. 1217-1231
SEQUENTIAL TEST-GENERATION AND SYNTHESIS FOR TESTABILITY AT THE REGISTER-TRANSFER AND LOGIC LEVELS
Authors: GHOSH A DEVADAS S NEWTON AR
Citation: A. Ghosh et al., SEQUENTIAL TEST-GENERATION AND SYNTHESIS FOR TESTABILITY AT THE REGISTER-TRANSFER AND LOGIC LEVELS, IEEE transactions on computer-aided design of integrated circuits and systems, 12(5), 1993, pp. 579-598
COMPARING 2-LEVEL AND ORDERED BINARY DECISION DIAGRAM REPRESENTATIONSOF LOGIC FUNCTIONS
Authors: DEVADAS S
Citation: S. Devadas, COMPARING 2-LEVEL AND ORDERED BINARY DECISION DIAGRAM REPRESENTATIONSOF LOGIC FUNCTIONS, IEEE transactions on computer-aided design of integrated circuits and systems, 12(5), 1993, pp. 722-723
COMPUTATION OF FLOATING MODE DELAY IN COMBINATIONAL-CIRCUITS - THEORYAND ALGORITHMS
Authors: DEVADAS S KEUTZER K MALIK S
Citation: S. Devadas et al., COMPUTATION OF FLOATING MODE DELAY IN COMBINATIONAL-CIRCUITS - THEORYAND ALGORITHMS, IEEE transactions on computer-aided design of integrated circuits and systems, 12(12), 1993, pp. 1913-1923
COMPUTATION OF FLOATING MODE DELAY IN COMBINATIONAL-CIRCUITS - PRACTICE AND IMPLEMENTATION
Authors: DEVADAS S KEUTZER K MALIK S WANG A
Citation: S. Devadas et al., COMPUTATION OF FLOATING MODE DELAY IN COMBINATIONAL-CIRCUITS - PRACTICE AND IMPLEMENTATION, IEEE transactions on computer-aided design of integrated circuits and systems, 12(12), 1993, pp. 1924-1936
Risultati: 1-25 | 26-27