Citation: Ml. Chang et Ws. Feng, A RECURSIVE ALGORITHM FOR ESTIMATING THE INTERNAL CHARGE SHARING EFFECT IN RC TREE CIRCUITS, IEICE transactions on fundamentals of electronics, communications and computer science, E81A(5), 1998, pp. 913-923
Citation: M. Chang et al., AN ALGORITHM FOR ESTIMATING BOTTLENECK EFFECT IN SERIES-PARALLEL TREECIRCUITS, IEICE transactions on fundamentals of electronics, communications and computer science, E81A(11), 1998, pp. 2400-2406
Citation: Ml. Chang et al., WAVE-FORM APPROXIMATION TECHNIQUE FOR CMOS GATES IN THE SWITCH-LEVEL TIMING SIMULATOR BTS, Zhongguo gongcheng xuekan, 21(3), 1998, pp. 255-268
Citation: By. Ma et al., DESIGN AND IMPLEMENTATION OF A SENSORLESS SWITCHED RELUCTANCE DRIVE SYSTEM, IEEE transactions on aerospace and electronic systems, 34(4), 1998, pp. 1193-1207
Citation: Wj. Ho et al., ECONOMIC UPS STRUCTURE WITH PHASE-CONTROLLED BATTERY CHARGER AND INPUT-POWER-FACTOR IMPROVEMENT, IEE proceedings. Electric power applications, 144(4), 1997, pp. 221-226
Citation: Wj. Chen et Ws. Feng, PATTERN-BASED MAXIMAL POWER ESTIMATION FOR VLSI CHIP DESIGN, IEICE transactions on fundamentals of electronics, communications and computer science, E80A(11), 1997, pp. 2300-2307
Citation: Sc. Fang et al., A NEW DIRECT DESIGN FOR 3-INPUT XOR FUNCTION ON THE TRANSISTOR LEVEL, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 43(4), 1996, pp. 343-348
Citation: M. Chang et al., ALGORITHM-BASED ON MODIFIED THREADED BINARY-TREE FOR ESTIMATING DELAYAFFECTED BY INTERNAL CHARGES IN CMO GATES, Electronics Letters, 32(20), 1996, pp. 1877-1879
Citation: Wj. Ho et al., OPTIMIZING SINGLE-PHASE PFC PRE-STAGED AC DC/AC TOPOLOGY VIA COMMON-NEUTRAL CONNECTION/, Electronics Letters, 32(17), 1996, pp. 1529-1530
Citation: Cj. Chen et Ws. Feng, RELAXATION-BASED TRANSIENT SENSITIVITY COMPUTATIONS FOR MOSFET CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(2), 1995, pp. 173-185
Citation: Jm. Wang et al., NEW EFFICIENT DESIGNS FOR XOR AND XNOR FUNCTIONS ON THE TRANSISTOR LEVEL, IEEE journal of solid-state circuits, 29(7), 1994, pp. 780-786
Citation: Jjh. Wang et al., BINARY-TREE TIMING SIMULATION WITH CONSIDERATION OF INTERNAL CHARGES, IEE proceedings. Part E. Computers and digital techniques, 140(4), 1993, pp. 211-219