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Results:
1-8
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Results: 8
Authors:
CHUNG PY
HAJJ IN
Citation: Py. Chung et In. Hajj, DIAGNOSIS AND CORRECTION OF MULTIPLE LOGIC DESIGN ERRORS IN DIGITAL CIRCUITS, IEEE transactions on very large scale integration (VLSI) systems, 5(2), 1997, pp. 233-237
Authors:
RAMPRASAD S
SHANBHAG NR
HAJJ IN
Citation: S. Ramprasad et al., ANALYTICAL ESTIMATION OF SIGNAL TRANSITION ACTIVITY FROM WORD-LEVEL STATISTICS, IEEE transactions on computer-aided design of integrated circuits and systems, 16(7), 1997, pp. 718-733
Authors:
LI PC
HAJJ IN
Citation: Pc. Li et In. Hajj, COMPUTER-AIDED REDESIGN OF VLSI CIRCUITS FOR HOT-CARRIER RELIABILITY, IEEE transactions on computer-aided design of integrated circuits and systems, 15(5), 1996, pp. 453-464
Authors:
KRIPLANI H
NAJM FN
HAJJ IN
Citation: H. Kriplani et al., PATTERN INDEPENDENT MAXIMUM CURRENT ESTIMATION IN POWER AND GROUND BUSES OF CMOS VLSI CIRCUITS - ALGORITHMS, SIGNAL CORRELATIONS, AND THEIRRESOLUTION, IEEE transactions on computer-aided design of integrated circuits and systems, 14(8), 1995, pp. 998-1012
Authors:
LEE T
CHUANG WT
HAJJ IN
FUCHS WK
Citation: T. Lee et al., CIRCUIT-LEVEL DICTIONARIES OF CMOS BRIDGING FAULTS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(5), 1995, pp. 596-603
Authors:
CHUANG WT
SAPATNEKAR SS
HAJJ IN
Citation: Wt. Chuang et al., TIMING AND AREA OPTIMIZATION FOR STANDARD-CELL VLSI CIRCUIT-DESIGN, IEEE transactions on computer-aided design of integrated circuits and systems, 14(3), 1995, pp. 308-320
Authors:
LI PC
STAMOULIS GI
HAJJ IN
Citation: Pc. Li et al., A PROBABILISTIC TIMING APPROACH TO HOT-CARRIER EFFECT ESTIMATION, IEEE transactions on computer-aided design of integrated circuits and systems, 13(10), 1994, pp. 1223-1234
Authors:
YANG AT
CHANG YH
SAAB DG
HAJJ IN
Citation: At. Yang et al., SWITCH-LEVEL TIMING SIMULATION OF BIPOLAR ECL CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 12(4), 1993, pp. 516-530
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