Authors: Lin, PF Kuo, JB

Citation: Pf. Lin et Jb. Kuo, A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell, IEEE J SOLI, 36(4), 2001, pp. 666-675

Authors: Liu, SC Wu, FA Kuo, JB

Citation: Sc. Liu et al., A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOICMOS dynamic-threshold (DTMOS) techniques, IEEE J SOLI, 36(4), 2001, pp. 712-716

Authors: Huang, YM Kuo, JB

Citation: Ym. Huang et Jb. Kuo, A high-speed conditional carry select (CCS) adder circuit with a successively incremented carry number block (SICNB) structure for low-voltage VLSI implementation, IEEE CIR-II, 47(10), 2000, pp. 1074-1079

Authors: Lin, SC Kuo, JB Huang, KT Sun, SW

Citation: Sc. Lin et al., A closed-form back-gate-bias related inverse narrow-channel effect model for deep-submicron VLSI CMOS devices using shallow trench isolation, IEEE DEVICE, 47(4), 2000, pp. 725-733

Authors: Lou, JH Kuo, JB

Citation: Jh. Lou et Jb. Kuo, A 1.5-V CMOS all-N-logic true-single-phase bootstrapped dynamic-logic circuit suitable for low supply voltage and high-speed pipelined system operation, IEEE CIR-II, 46(5), 1999, pp. 628-631

Authors: Lin, SC Kuo, JB

Citation: Sc. Lin et Jb. Kuo, Temperature-dependent kink effect model for partially-depleted SOI NMOS devices, IEEE DEVICE, 46(1), 1999, pp. 254-258