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Results: 1-25 | 26-32
Results: 1-25/32
Voltage-mode MOSFET-C filters using operational transresistance amplifiers(OTRAs) with reduced parasitic capacitance effect
Authors: Chen, JJ Tsao, HW Liu, SI
Citation: Jj. Chen et al., Voltage-mode MOSFET-C filters using operational transresistance amplifiers(OTRAs) with reduced parasitic capacitance effect, IEE P-CIRC, 148(5), 2001, pp. 242-249
Pipeline direct digital frequency synthesiser using decomposition method
Authors: Liu, SI Yu, TB Tsao, HW
Citation: Si. Liu et al., Pipeline direct digital frequency synthesiser using decomposition method, IEE P-CIRC, 148(3), 2001, pp. 141-144
Low-voltage CMOS frequency synthesizer for ERMES pager application
Authors: Hsu, JM Dehng, GK Yang, CY Yang, CY Liu, SI
Citation: Jm. Hsu et al., Low-voltage CMOS frequency synthesizer for ERMES pager application, IEEE CIR-II, 48(9), 2001, pp. 826-834
Low-voltage analog tripler circuit
Authors: Chang, CC Liu, SI Hwang, YS
Citation: Cc. Chang et al., Low-voltage analog tripler circuit, ANALOG IN C, 26(2), 2001, pp. 125-128
A 2.4 GHz low voltage CMOS down-conversion double-balanced mixer
Authors: Tang, CC Wu, CH Feng, WS Liu, SI
Citation: Cc. Tang et al., A 2.4 GHz low voltage CMOS down-conversion double-balanced mixer, IEICE TR EL, E84C(8), 2001, pp. 1084-1091
A one-wire approach for skew-compensating clock distribution based on bidirectional techniques
Authors: Yang, CY Liu, SI
Citation: Cy. Yang et Si. Liu, A one-wire approach for skew-compensating clock distribution based on bidirectional techniques, IEEE J SOLI, 36(2), 2001, pp. 266-272
A fast-lock mixed-mode DLL using a 2-b SAR algorithm
Authors: Dehng, GK Lin, JW Liu, SI
Citation: Gk. Dehng et al., A fast-lock mixed-mode DLL using a 2-b SAR algorithm, IEEE J SOLI, 36(10), 2001, pp. 1464-1471
A CMOS 400-Mb/s serial link for AS-memory systems using a PWM scheme
Authors: Chen, WH Dehng, GK Chen, JW Liu, SI
Citation: Wh. Chen et al., A CMOS 400-Mb/s serial link for AS-memory systems using a PWM scheme, IEEE J SOLI, 36(10), 2001, pp. 1498-1505
CMOS oversampling Delta Sigma magnetic-to-digital converters
Authors: Kuo, CH Chen, SL Ho, LA Liu, SI
Citation: Ch. Kuo et al., CMOS oversampling Delta Sigma magnetic-to-digital converters, IEEE J SOLI, 36(10), 2001, pp. 1582-1586
An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique
Authors: Liu, MH Liu, SI
Citation: Mh. Liu et Si. Liu, An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique, IEEE J SOLI, 36(1), 2001, pp. 122-128
Low-voltage CMOS low-noise amplifier using planar-interleaved transformer
Authors: Tang, CC Liu, SI
Citation: Cc. Tang et Si. Liu, Low-voltage CMOS low-noise amplifier using planar-interleaved transformer, ELECTR LETT, 37(8), 2001, pp. 497-498
Integrator and differentiator with time constant multiplication using current feedback amplifier
Authors: Lee, JL Liu, SI
Citation: Jl. Lee et Si. Liu, Integrator and differentiator with time constant multiplication using current feedback amplifier, ELECTR LETT, 37(6), 2001, pp. 331-333
CMOS current-mode exponential-control variable-gain amplifier
Authors: Chang, CC Lin, ML Liu, SI
Citation: Cc. Chang et al., CMOS current-mode exponential-control variable-gain amplifier, ELECTR LETT, 37(14), 2001, pp. 868-869
Three types of 2-D lateral magnetoresistive sensors with p(+)-implant confinement
Authors: Sung, GM Wei, JF Liu, SI
Citation: Gm. Sung et al., Three types of 2-D lateral magnetoresistive sensors with p(+)-implant confinement, IEE P-CIRC, 147(3), 2000, pp. 158-164
Risk factors of mortality in perforated peptic ulcer
Authors: Chou, NH Mok, KT Chang, HT Liu, SI Tsai, CC Wang, BW Chen, IS
Citation: Nh. Chou et al., Risk factors of mortality in perforated peptic ulcer, EURO J SURG, 166(2), 2000, pp. 149-153
A CMOS pulse-shrinking delay element for time interval measurement
Authors: Chen, PK Liu, SI Wu, JS
Citation: Pk. Chen et al., A CMOS pulse-shrinking delay element for time interval measurement, IEEE CIR-II, 47(9), 2000, pp. 954-958
Pseudo-exponential function for MOSFETs in saturation
Authors: Chang, CC Liu, SI
Citation: Cc. Chang et Si. Liu, Pseudo-exponential function for MOSFETs in saturation, IEEE CIR-II, 47(11), 2000, pp. 1318-1321
Clock-deskew buffer using a SAR-Controlled delay-locked loop
Authors: Dehng, GK Hsu, JM Yang, CY Liu, SI
Citation: Gk. Dehng et al., Clock-deskew buffer using a SAR-Controlled delay-locked loop, IEEE J SOLI, 35(8), 2000, pp. 1128-1136
A 900-MHz 1-V CMOS frequency synthesizer
Authors: Dehng, GK Yang, CY Hsu, JM Liu, SI
Citation: Gk. Dehng et al., A 900-MHz 1-V CMOS frequency synthesizer, IEEE J SOLI, 35(8), 2000, pp. 1211-1214
A double-sampling pseudo-two-path bandpass Delta Sigma modulator
Authors: Liu, SI Kuo, CH Tsai, RY Wu, JS
Citation: Si. Liu et al., A double-sampling pseudo-two-path bandpass Delta Sigma modulator, IEEE J SOLI, 35(2), 2000, pp. 276-280
Fast-switching frequency synthesizer with a discriminator-aided phase detector
Authors: Yang, CY Liu, SI
Citation: Cy. Yang et Si. Liu, Fast-switching frequency synthesizer with a discriminator-aided phase detector, IEEE J SOLI, 35(10), 2000, pp. 1445-1452
Current-mode full-wave rectifier and vector summation circuit
Authors: Chang, CC Liu, SI
Citation: Cc. Chang et Si. Liu, Current-mode full-wave rectifier and vector summation circuit, ELECTR LETT, 36(19), 2000, pp. 1599-1600
Current-mode pseudo-exponential circuit with tunable input range
Authors: Chang, CC Liu, SI
Citation: Cc. Chang et Si. Liu, Current-mode pseudo-exponential circuit with tunable input range, ELECTR LETT, 36(16), 2000, pp. 1335-1336
Realisation of exponential V-I converter using composite NMOS transistors
Authors: Liu, WS Chang, CC Liu, SI
Citation: Ws. Liu et al., Realisation of exponential V-I converter using composite NMOS transistors, ELECTR LETT, 36(1), 2000, pp. 8-10
SPICE macro model for MAGFET and its applications
Authors: Liu, SI Wei, JF Sung, GM
Citation: Si. Liu et al., SPICE macro model for MAGFET and its applications, IEEE CIR-II, 46(4), 1999, pp. 370-375
Risultati: 1-25 | 26-32