AAAAAA

   
Results: 1-14 |
Results: 14
SMART SUBSTRATE MCMS
Authors: GATTIKER AE MALY W
Citation: Ae. Gattiker et W. Maly, SMART SUBSTRATE MCMS, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 10(1-2), 1997, pp. 39-53
SIMULATION OF YIELD COST LEARNING-CURVES WITH Y4/
Authors: NAG PK MALY W JACOBS HJ
Citation: Pk. Nag et al., SIMULATION OF YIELD COST LEARNING-CURVES WITH Y4/, IEEE transactions on semiconductor manufacturing, 10(2), 1997, pp. 256-266
BEHAVIOR AND TESTABILITY PRESERVATION UNDER THE RETIMING TRANSFORMATION
Authors: ELMALEH A MARCHOK TE RAJSKI J MALY W
Citation: A. Elmaleh et al., BEHAVIOR AND TESTABILITY PRESERVATION UNDER THE RETIMING TRANSFORMATION, IEEE transactions on computer-aided design of integrated circuits and systems, 16(5), 1997, pp. 528-543
RAPID FAILURE ANALYSIS USING CONTAMINATION-DEFECT-FAULT (CDF) SIMULATION
Authors: KHARE J MALY W
Citation: J. Khare et W. Maly, RAPID FAILURE ANALYSIS USING CONTAMINATION-DEFECT-FAULT (CDF) SIMULATION, IEEE transactions on semiconductor manufacturing, 9(4), 1996, pp. 518-526
THE FUTURE OF IC DESIGN, TESTING, AND MANUFACTURING
Authors: MALY W
Citation: W. Maly, THE FUTURE OF IC DESIGN, TESTING, AND MANUFACTURING, IEEE design & test of computers, 13(4), 1996, pp. 8
A D-AND-T ROUND-TABLE - DEEP-SUBMICRON TEST IN COOPERATION WITH THE TEST TECHNOLOGY TECHNICAL COMMITTEE
Authors: ZORIAN Y BUTLER KM MALY W KOENEMANN BK NEEDHAM W AITKEN RC CAMPBELL RL
Citation: Y. Zorian et al., A D-AND-T ROUND-TABLE - DEEP-SUBMICRON TEST IN COOPERATION WITH THE TEST TECHNOLOGY TECHNICAL COMMITTEE, IEEE design & test of computers, 13(3), 1996, pp. 102-108
A COMPLEXITY ANALYSIS OF SEQUENTIAL ATPG
Authors: MARCHOK TE ELMALEH A MALY W RAJSKI J
Citation: Te. Marchok et al., A COMPLEXITY ANALYSIS OF SEQUENTIAL ATPG, IEEE transactions on computer-aided design of integrated circuits and systems, 15(11), 1996, pp. 1409-1423
CRITICAL AREA ANALYSIS FOR DESIGN-BASED YIELD IMPROVEMENT OF VLSI CIRCUITS
Authors: SCHMITTLANDSIEDEL D KEITELSCHULZ D KHARE J GRIEP S MALY W
Citation: D. Schmittlandsiedel et al., CRITICAL AREA ANALYSIS FOR DESIGN-BASED YIELD IMPROVEMENT OF VLSI CIRCUITS, Quality and reliability engineering international, 11(4), 1995, pp. 227-232
TESTABILITY IMPLICATIONS OF PERFORMANCE-DRIVEN LOGIC SYNTHESIS
Authors: MARCHOK TE ELMALEH A RAJSKI J MALY W
Citation: Te. Marchok et al., TESTABILITY IMPLICATIONS OF PERFORMANCE-DRIVEN LOGIC SYNTHESIS, IEEE design & test of computers, 12(2), 1995, pp. 32-39
SPECIAL SECTION ON THE 12TH IEEE VLSI SYMPOSIUM
Authors: MALY W ZORIAN Y
Citation: W. Maly et Y. Zorian, SPECIAL SECTION ON THE 12TH IEEE VLSI SYMPOSIUM, IEEE transactions on computer-aided design of integrated circuits and systems, 14(5), 1995, pp. 529-530
EXTRACTION OF DEFECT SIZE DISTRIBUTIONS IN AN IC LAYER USING TEST STRUCTURE DATA
Authors: KHARE JB MALY W THOMAS ME
Citation: Jb. Khare et al., EXTRACTION OF DEFECT SIZE DISTRIBUTIONS IN AN IC LAYER USING TEST STRUCTURE DATA, IEEE transactions on semiconductor manufacturing, 7(3), 1994, pp. 354-368
TEST ECONOMICS - IN COOPERATION WITH THE 1994 EUROPEAN DESIGN AND TEST CONFERENCE
Authors: GHEEWALA T MALY W ZORIAN Y BAKER K ILLMAN R AMBLER T
Citation: T. Gheewala et al., TEST ECONOMICS - IN COOPERATION WITH THE 1994 EUROPEAN DESIGN AND TEST CONFERENCE, IEEE design & test of computers, 11(3), 1994, pp. 70-77
SMART-SUBSTRATE MULTICHIP-MODULE SYSTEMS
Authors: MALY W FELTHAM DBI GATTIKER AE HOBAUGH MD BACKUS K THOMAS ME
Citation: W. Maly et al., SMART-SUBSTRATE MULTICHIP-MODULE SYSTEMS, IEEE design & test of computers, 11(2), 1994, pp. 64-73
FAILURE ANALYSIS OF HIGH-DENSITY CMOS SRAMS - USING REALISTIC DEFECT MODELING AND IDDQ TESTING
Authors: NAIK S AGRICOLA F MALY W
Citation: S. Naik et al., FAILURE ANALYSIS OF HIGH-DENSITY CMOS SRAMS - USING REALISTIC DEFECT MODELING AND IDDQ TESTING, IEEE design & test of computers, 10(2), 1993, pp. 13-23
Risultati: 1-14 |