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Results: 1-21 |
Results: 21
POWER DISTRIBUTION SYNTHESIS FOR VLSI
Authors: VITTAL A MAREKSADOWSKA M
Citation: A. Vittal et M. Mareksadowska, POWER DISTRIBUTION SYNTHESIS FOR VLSI, VLSI design, 7(1), 1998, pp. 59-72
TEST-POINT INSERTION - SCAN PATHS THROUGH FUNCTIONAL LOGIC
Authors: LIN CC MAREKSADOWSKA M CHENG KT LEE MTC
Citation: Cc. Lin et al., TEST-POINT INSERTION - SCAN PATHS THROUGH FUNCTIONAL LOGIC, IEEE transactions on computer-aided design of integrated circuits and systems, 17(9), 1998, pp. 838-851
COST-FREE SCAN - A LOW-OVERHEAD SCAN PATH DESIGN
Authors: LIN CC MAREKSADOWSKA M LEE MTC CHEN KC
Citation: Cc. Lin et al., COST-FREE SCAN - A LOW-OVERHEAD SCAN PATH DESIGN, IEEE transactions on computer-aided design of integrated circuits and systems, 17(9), 1998, pp. 852-861
A HYBRID METHODOLOGY FOR SWITCHING ACTIVITIES ESTIMATION
Authors: CHENG DI CHENG KT WANG DC MAREKSADOWSKA M
Citation: Di. Cheng et al., A HYBRID METHODOLOGY FOR SWITCHING ACTIVITIES ESTIMATION, IEEE transactions on computer-aided design of integrated circuits and systems, 17(4), 1998, pp. 357-366
ON REGULAR SEGMENTED 2-D FPGA ROUTING
Authors: WU YL MAREKSADOWSKA M
Citation: Yl. Wu et M. Mareksadowska, ON REGULAR SEGMENTED 2-D FPGA ROUTING, IEICE transactions on fundamentals of electronics, communications and computer science, E80A(10), 1997, pp. 1871-1877
LOW-POWER BUFFERED CLOCK TREE DESIGN
Authors: VITTAL A MAREKSADOWSKA M
Citation: A. Vittal et M. Mareksadowska, LOW-POWER BUFFERED CLOCK TREE DESIGN, IEEE transactions on computer-aided design of integrated circuits and systems, 16(9), 1997, pp. 965-975
POSTLAYOUT LOGIC RESTRUCTURING USING ALTERNATIVE WIRES
Authors: CHANG SC CHENG KT WOO NS MAREKSADOWSKA M
Citation: Sc. Chang et al., POSTLAYOUT LOGIC RESTRUCTURING USING ALTERNATIVE WIRES, IEEE transactions on computer-aided design of integrated circuits and systems, 16(6), 1997, pp. 587-596
ROUTING FOR ARRAY-TYPE FPGAS
Authors: WU YL MAREKSADOWSKA M
Citation: Yl. Wu et M. Mareksadowska, ROUTING FOR ARRAY-TYPE FPGAS, IEEE transactions on computer-aided design of integrated circuits and systems, 16(5), 1997, pp. 506-518
ON DESIGNING UNIVERSAL LOGIC BLOCKS AND THEIR APPLICATION TO FPGA DESIGN
Authors: LIN CC MAREKSADOWSKA M GATLIN D
Citation: Cc. Lin et al., ON DESIGNING UNIVERSAL LOGIC BLOCKS AND THEIR APPLICATION TO FPGA DESIGN, IEEE transactions on computer-aided design of integrated circuits and systems, 16(5), 1997, pp. 519-527
CROSSTALK REDUCTION FOR VLSI
Authors: VITTAL A MAREKSADOWSKA M
Citation: A. Vittal et M. Mareksadowska, CROSSTALK REDUCTION FOR VLSI, IEEE transactions on computer-aided design of integrated circuits and systems, 16(3), 1997, pp. 290-298
BOOLEAN FUNCTIONS CLASSIFICATION VIA FIXED POLARITY REED-MULLER FORMS
Authors: TSAI CC MAREKSADOWSKA M
Citation: Cc. Tsai et M. Mareksadowska, BOOLEAN FUNCTIONS CLASSIFICATION VIA FIXED POLARITY REED-MULLER FORMS, I.E.E.E. transactions on computers, 46(2), 1997, pp. 173-186
PERTURB AND SIMPLIFY - MULTILEVEL BOOLEAN NETWORK OPTIMIZER
Authors: CHANG SC MAREKSADOWSKA M CHENG KT
Citation: Sc. Chang et al., PERTURB AND SIMPLIFY - MULTILEVEL BOOLEAN NETWORK OPTIMIZER, IEEE transactions on computer-aided design of integrated circuits and systems, 15(12), 1996, pp. 1494-1504
TECHNOLOGY MAPPING FOR TLU FPGAS BASED ON DECOMPOSITION OF BINARY DECISION DIAGRAMS
Authors: CHANG SC MAREKSADOWSKA M HWANG TT
Citation: Sc. Chang et al., TECHNOLOGY MAPPING FOR TLU FPGAS BASED ON DECOMPOSITION OF BINARY DECISION DIAGRAMS, IEEE transactions on computer-aided design of integrated circuits and systems, 15(10), 1996, pp. 1226-1236
GRAPH-BASED ANALYSIS OF 2-D FPGA ROUTING
Authors: WU YL TSUKIYAMA S MAREKSADOWSKA M
Citation: Yl. Wu et al., GRAPH-BASED ANALYSIS OF 2-D FPGA ROUTING, IEEE transactions on computer-aided design of integrated circuits and systems, 15(1), 1996, pp. 33-44
GENERALIZED REED-MULLER FORMS AS A TOOL TO DETECT SYMMETRIES
Authors: TSAI CC MAREKSADOWSKA M
Citation: Cc. Tsai et M. Mareksadowska, GENERALIZED REED-MULLER FORMS AS A TOOL TO DETECT SYMMETRIES, I.E.E.E. transactions on computers, 45(1), 1996, pp. 33-40
SPECIAL SECTION ON VLSI DESIGN AND CAD ALGORITHMS - FOREWORD
Authors: MAREKSADOWSKA M TSUKIYAMA S
Citation: M. Mareksadowska et S. Tsukiyama, SPECIAL SECTION ON VLSI DESIGN AND CAD ALGORITHMS - FOREWORD, IEICE transactions on fundamentals of electronics, communications and computer science, E78A(12), 1995, pp. 1689-1690
THE CROSSING DISTRIBUTION PROBLEM
Authors: MAREKSADOWSKA M SARRAFZADEH M
Citation: M. Mareksadowska et M. Sarrafzadeh, THE CROSSING DISTRIBUTION PROBLEM, IEEE transactions on computer-aided design of integrated circuits and systems, 14(4), 1995, pp. 423-433
UNTITLED
Authors: MAREKSADOWSKA M
Citation: M. Mareksadowska, UNTITLED, IEEE transactions on computer-aided design of integrated circuits and systems, 14(10), 1995, pp. 1181-1181
LOGIC SYNTHESIS FOR ENGINEERING CHANGE
Authors: CHEN KC LIN CC MAREKSADOWSKA M
Citation: Kc. Chen et al., LOGIC SYNTHESIS FOR ENGINEERING CHANGE, Fujitsu Scientific and Technical Journal, 31(2), 1995, pp. 115-124
MINIMIZATION OF FIXED-POLARITY AND XOR CANONICAL NETWORKS/
Authors: TSAI CC MAREKSADOWSKA M
Citation: Cc. Tsai et M. Mareksadowska, MINIMIZATION OF FIXED-POLARITY AND XOR CANONICAL NETWORKS/, IEE proceedings. Computers and digital techniques, 141(6), 1994, pp. 369-374
STEPWISE EQUIVALENT CONDUCTANCE CIRCUIT SIMULATION TECHNIQUE
Authors: LIN S KUH ES MAREKSADOWSKA M
Citation: S. Lin et al., STEPWISE EQUIVALENT CONDUCTANCE CIRCUIT SIMULATION TECHNIQUE, IEEE transactions on computer-aided design of integrated circuits and systems, 12(5), 1993, pp. 672-683
Risultati: 1-21 |