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Results: 1-9 |
Results: 9
A specification refinement methodology for power efficient partitioning ofdata-dominated algorithms within performance constraints
Authors: Masselos, K Danckaert, K Catthoor, F Zervas, N Goutis, CE De Man, H
Citation: K. Masselos et al., A specification refinement methodology for power efficient partitioning ofdata-dominated algorithms within performance constraints, J VLSI S P, 26(3), 2000, pp. 291-317
Low power architectures for digital signal processing
Authors: Masselos, K Merakos, P Stouraitis, T Goutis, CE
Citation: K. Masselos et al., Low power architectures for digital signal processing, J SYST ARCH, 46(7), 2000, pp. 551-571
Power efficient synthesis of sum-of-products computations
Authors: Masselos, K Goutis, CE
Citation: K. Masselos et Ce. Goutis, Power efficient synthesis of sum-of-products computations, UNIFIED LOW-POWER DESIGN FLOW FOR DATA-DOMINATED MULTI-MEDIA AND TELECOM APPLICATIONS, 2000, pp. 159-180
Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec
Authors: Danckaert, K Masselos, K Catthoor, F De Man, H
Citation: K. Danckaert et al., Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec, J SYST ARCH, 45(10), 1999, pp. 791-808
Computation reordering: A novel transformation for low power DSP synthesis
Authors: Masselos, K Merakos, P Stouraitis, T Goutis, CE
Citation: K. Masselos et al., Computation reordering: A novel transformation for low power DSP synthesis, VLSI DESIGN, 10(2), 1999, pp. 177-202
Novel techniques for bus power consumption reduction in realizations of sum-of-product computation
Authors: Masselos, K Merakos, P Stouraitis, T Goutis, CE
Citation: K. Masselos et al., Novel techniques for bus power consumption reduction in realizations of sum-of-product computation, IEEE VLSI, 7(4), 1999, pp. 492-497
Strategy for power-efficient design of parallel systems
Authors: Danckaert, K Masselos, K Catthoor, F De Man, HJ Goutis, C
Citation: K. Danckaert et al., Strategy for power-efficient design of parallel systems, IEEE VLSI, 7(2), 1999, pp. 258-265
Novel vector quantization based algorithms for low-power image coding and decoding
Authors: Masselos, K Merakos, P Stouraitis, T Goutis, CE
Citation: K. Masselos et al., Novel vector quantization based algorithms for low-power image coding and decoding, IEEE CIR-II, 46(2), 1999, pp. 193-198
Novel scheme for low-power classified vector quantisation image coding
Authors: Masselos, K Stouraitis, T Goutis, CE
Citation: K. Masselos et al., Novel scheme for low-power classified vector quantisation image coding, IEE P-VIS I, 145(6), 1998, pp. 408-414
Risultati: 1-9 |