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Results:
1-8
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Results: 8
Authors:
Kranitis, N
Paschalis, A
Gizopoulos, D
Psarakis, M
Zorian, Y
Citation: N. Kranitis et al., An effective deterministic BIST scheme for shifter/accumulator pairs in datapaths, J ELEC TEST, 17(2), 2001, pp. 97-107
Authors:
Kranitis, N
Gizopoulos, D
Paschalis, A
Psarakis, M
Zorian, Y
Citation: N. Kranitis et al., Power-/energy-efficient BIST schemes for processor data paths, IEEE DES T, 17(4), 2000, pp. 15-28
Authors:
Psarakis, M
Gizopoulos, D
Paschalis, A
Zorian, Y
Citation: M. Psarakis et al., Sequential fault modeling and test pattern generation for CMOS iterative logic arrays, IEEE COMPUT, 49(10), 2000, pp. 1083-1099
Authors:
Voyiatzis, I
Paschalis, A
Nikolos, D
Halatsis, C
Citation: I. Voyiatzis et al., An accumulator-based BIST approach for two-pattern testing, J ELEC TEST, 15(3), 1999, pp. 267-278
Authors:
Gizopoulos, D
Paschalis, A
Nikolos, D
Halatsis, C
Citation: D. Gizopoulos et al., On robust two-pattern testing of one-dimensional CMOS iterative logic arrays, INT J ELECT, 86(8), 1999, pp. 967-978
Authors:
Gizopoulos, D
Paschalis, A
Zorian, Y
Citation: D. Gizopoulos et al., An effective built-in self-test scheme for parallel multipliers, IEEE COMPUT, 48(9), 1999, pp. 936-950
Authors:
Psarakis, M
Gizopoulos, D
Paschalis, A
Citation: M. Psarakis et al., Test generation and fault simulation for cell fault model using stuck-at fault model based test tools, J ELEC TEST, 13(3), 1998, pp. 315-319
Authors:
Paschalis, A
Gaitanis, N
Gizopoulos, D
Kostarakis, P
Citation: A. Paschalis et al., A totally self-checking 1-out-of-3 code error indicator, J ELEC TEST, 13(1), 1998, pp. 61-66
Risultati:
1-8
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