AAAAAA

   
Results: 1-17 |
Results: 17
Power optimization of delay constrained circuits
Authors: Nayak, A Haldar, M Banerjee, P Chen, CH Sarrafzadeh, M
Citation: A. Nayak et al., Power optimization of delay constrained circuits, VLSI DESIGN, 12(2), 2001, pp. 125-138
On gate level power optimization using dual-supply voltages
Authors: Chen, CH Srivastava, A Sarrafzadeh, M
Citation: Ch. Chen et al., On gate level power optimization using dual-supply voltages, IEEE VLSI, 9(5), 2001, pp. 616-629
Fast floorplanning for effective prediction and construction
Authors: Ranjan, A Bazargan, K Ogrenci, S Sarrafzadeh, M
Citation: A. Ranjan et al., Fast floorplanning for effective prediction and construction, IEEE VLSI, 9(2), 2001, pp. 341-351
Timing driven gate duplication in technology independent phase
Authors: Srivastava, A Chen, CH Sarrafzadeh, M
Citation: A. Srivastava et al., Timing driven gate duplication in technology independent phase, IEICE T FUN, E84A(11), 2001, pp. 2673-2680
On the complexity of gate duplication
Authors: Srivastava, A Kastner, R Sarrafzadeh, M
Citation: A. Srivastava et al., On the complexity of gate duplication, IEEE COMP A, 20(9), 2001, pp. 1170-1176
Activity-driven clock design
Authors: Farrahi, AH Chen, CH Srivastava, A Tellez, G Sarrafzadeh, M
Citation: Ah. Farrahi et al., Activity-driven clock design, IEEE COMP A, 20(6), 2001, pp. 705-714
3-D floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems
Authors: Bazargan, K Kastner, R Sarrafzadeh, M
Citation: K. Bazargan et al., 3-D floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems, DES AUTOM E, 5(3-4), 2000, pp. 329-338
Fast template placement for reconfigurable computing systems
Authors: Bazargan, K Kastner, R Sarrafzadeh, M
Citation: K. Bazargan et al., Fast template placement for reconfigurable computing systems, IEEE DES T, 17(1), 2000, pp. 68-83
Fundamental CAD algorithms
Authors: Breuer, MA Sarrafzadeh, M Somenzi, F
Citation: Ma. Breuer et al., Fundamental CAD algorithms, IEEE COMP A, 19(12), 2000, pp. 1449-1475
Congestion minimization during placement
Authors: Wang, MG Yang, XJ Sarrafzadeh, M
Citation: Mg. Wang et al., Congestion minimization during placement, IEEE COMP A, 19(10), 2000, pp. 1140-1148
On the power of logic resynthesis
Authors: Lin, WL Farrahi, AH Sarrafzadeh, M
Citation: Wl. Lin et al., On the power of logic resynthesis, SIAM J COMP, 29(4), 2000, pp. 1257-1289
Placement with incomplete data
Authors: Wang, MG Banerjee, P Sarrafzadeh, M
Citation: Mg. Wang et al., Placement with incomplete data, VLSI DESIGN, 10(1), 1999, pp. 57-70
Evaluation and optimization of replication algorithms for logic bipartitioning
Authors: Enos, M Hauck, S Sarrafzadeh, M
Citation: M. Enos et al., Evaluation and optimization of replication algorithms for logic bipartitioning, IEEE COMP A, 18(9), 1999, pp. 1237-1248
Guest Editorial
Authors: Sarrafzadeh, M Wong, MDF
Citation: M. Sarrafzadeh et Mdf. Wong, Guest Editorial, IEEE COMP A, 18(4), 1999, pp. 373-374
Nostradamus: A floorplanner of uncertain designs
Authors: Bazargan, K Kim, S Sarrafzadeh, M
Citation: K. Bazargan et al., Nostradamus: A floorplanner of uncertain designs, IEEE COMP A, 18(4), 1999, pp. 389-397
Two-way and multiway partitioning of a set of intervals for clique-width maximization
Authors: Farrahi, AH Lee, DT Sarrafzadeh, M
Citation: Ah. Farrahi et al., Two-way and multiway partitioning of a set of intervals for clique-width maximization, ALGORITHMIC, 23(3), 1999, pp. 187-210
On the sum coloring problem on interval graphs
Authors: Nicoloso, S Sarrafzadeh, M Song, X
Citation: S. Nicoloso et al., On the sum coloring problem on interval graphs, ALGORITHMIC, 23(2), 1999, pp. 109-126
Risultati: 1-17 |