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Results: 1-17 |
Results: 17
A bus delay reduction technique considering crosstalk
Authors: Hirose, K Yasuura, H
Citation: K. Hirose et H. Yasuura, A bus delay reduction technique considering crosstalk, ELEC C JP 3, 85(1), 2002, pp. 24-31
High-performance hardware design and implementation of genetic algorithms
Authors: Shackleford, B Okushi, E Yasuda, M Koizumi, H Seo, K Iwamoto, T Yasuura, H
Citation: B. Shackleford et al., High-performance hardware design and implementation of genetic algorithms, STUD FUZZ S, 74, 2001, pp. 53-87
Optimization of test accesses with a combined BIST and external test scheme
Authors: Sugihara, M Yasuura, H
Citation: M. Sugihara et H. Yasuura, Optimization of test accesses with a combined BIST and external test scheme, IEICE T FUN, E84A(11), 2001, pp. 2731-2738
Towards the system LSI design technology
Authors: Yasuura, H
Citation: H. Yasuura, Towards the system LSI design technology, IEICE T FUN, E84A(1), 2001, pp. 91-97
Software energy reduction techniques for variable-voltage processors
Authors: Okuma, T Ishihara, T Yasuura, H
Citation: T. Okuma et al., Software energy reduction techniques for variable-voltage processors, IEEE DES T, 18(2), 2001, pp. 31-41
Evaluation of a floating dosage form of nicardipine hydrochloride and hydroxypropylmethylcellulose acetate succinate prepared using a twin-screw extruder
Authors: Nakamichi, K Yasuura, H Fukui, H Oka, M Izumi, S
Citation: K. Nakamichi et al., Evaluation of a floating dosage form of nicardipine hydrochloride and hydroxypropylmethylcellulose acetate succinate prepared using a twin-screw extruder, INT J PHARM, 218(1-2), 2001, pp. 103-112
Untitled
Authors: Yasuura, H
Citation: H. Yasuura, Untitled, DES AUTOM E, 5(2), 2000, pp. 127-127
Flexible system LSI for embedded systems and its optimization techniques
Authors: Inoue, A Ishihara, T Yasuura, H
Citation: A. Inoue et al., Flexible system LSI for embedded systems and its optimization techniques, DES AUTOM E, 5(2), 2000, pp. 179-205
System LSI design methods for low power LSIs
Authors: Yasuura, H Ishihara, T
Citation: H. Yasuura et T. Ishihara, System LSI design methods for low power LSIs, IEICE TR EL, E83C(2), 2000, pp. 143-152
Synthesis of minimum-cost multilevel logic networks via genetic algorithm
Authors: Shackleford, B Okushi, E Yasuda, M Koizumi, H Seo, K Yasuura, H
Citation: B. Shackleford et al., Synthesis of minimum-cost multilevel logic networks via genetic algorithm, IEICE T FUN, E83A(12), 2000, pp. 2528-2537
Special section on VLSI design and CAD algorithms - Foreword
Authors: Yasuura, H Koyanagi, M
Citation: H. Yasuura et M. Koyanagi, Special section on VLSI design and CAD algorithms - Foreword, IEICE T FUN, E82A(11), 1999, pp. 2317-2317
A memory power optimization technique for application specific embedded systems
Authors: Ishihara, T Yasuura, H
Citation: T. Ishihara et H. Yasuura, A memory power optimization technique for application specific embedded systems, IEICE T FUN, E82A(11), 1999, pp. 2366-2374
Module selection using manufacturing information
Authors: Tomiyama, H Yasuura, H
Citation: H. Tomiyama et H. Yasuura, Module selection using manufacturing information, IEICE T FUN, E81A(12), 1998, pp. 2576-2584
Program slicing on VHDL descriptions and its evaluation
Authors: Ichinose, S Iwaihara, M Yasuura, H
Citation: S. Ichinose et al., Program slicing on VHDL descriptions and its evaluation, IEICE T FUN, E81A(12), 1998, pp. 2585-2594
Language and compiler for optimizing datapath widths of embedded systems
Authors: Inoue, A Tomiyama, H Okuma, T Kanbara, H Yasuura, H
Citation: A. Inoue et al., Language and compiler for optimizing datapath widths of embedded systems, IEICE T FUN, E81A(12), 1998, pp. 2595-2604
Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches
Authors: Tomiyama, H Ishihara, T Inoue, A Yasuura, H
Citation: H. Tomiyama et al., Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches, IEICE T FUN, E81A(12), 1998, pp. 2621-2629
A test methodology for core-based system LSls
Authors: Sugihara, M Date, H Yasuura, H
Citation: M. Sugihara et al., A test methodology for core-based system LSls, IEICE T FUN, E81A(12), 1998, pp. 2640-2645
Risultati: 1-17 |