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Results: 126-150/339
Authors:
Wang, MG
Banerjee, P
Sarrafzadeh, M
Citation: Mg. Wang et al., Placement with incomplete data, VLSI DESIGN, 10(1), 1999, pp. 57-70
Authors:
Xu, J
Guo, PN
Cheng, CK
Citation: J. Xu et al., Empirical study of block placement by cluster refinement, VLSI DESIGN, 10(1), 1999, pp. 71-86
Authors:
Nam, SH
Cho, JD
Wagner, D
Citation: Sh. Nam et al., Lower-power and min-crosstalk channel routing for deep-submicron layout design, VLSI DESIGN, 10(1), 1999, pp. 87-97
Authors:
Alpert, CJ
Caldwell, AE
Chan, TF
Huang, DJH
Kahng, AB
Markov, IL
Moroz, MS
Citation: Cj. Alpert et al., Analytical engines are unnecessary in top-down partitioning-based placement, VLSI DESIGN, 10(1), 1999, pp. 99-116
Authors:
Kim, W
Shin, H
Citation: W. Kim et H. Shin, Hierarchy restructuring for hierarchical LVS comparison, VLSI DESIGN, 10(1), 1999, pp. 117-125
Authors:
Cho, JD
Citation: Jd. Cho, Special issue: Physical design automation in deep submicron - Preface, VLSI DESIGN, 10(1), 1999, pp. I-III
Authors:
VERDIER FS
ZAVIDOVIQUE B
Citation: Fs. Verdier et B. Zavidovique, A HIGH-LEVEL SYNTHESIS SYSTEM FOR VLSI IMAGE-PROCESSING APPLICATIONS, VLSI design (Print), 7(4), 1998, pp. 321-336
Authors:
MANDAL CA
CHAKRABARTI PP
GHOSE S
Citation: Ca. Mandal et al., COMPLEXITY OF SCHEDULING IN HIGH-LEVEL SYNTHESIS, VLSI design (Print), 7(4), 1998, pp. 337-346
Authors:
RAVIKUMAR CP
SHARMA N
Citation: Cp. Ravikumar et N. Sharma, TESTABILITY-DRIVEN LAYOUT OF COMBINATIONAL-CIRCUITS, VLSI design (Print), 7(4), 1998, pp. 347-352
Authors:
NAG S
ROY K
Citation: S. Nag et K. Roy, PERFORMANCE AND WIRABILITY DRIVEN LAYOUT FOR ROW-BASED FPGAS, VLSI design (Print), 7(4), 1998, pp. 353-364
Authors:
GONZALEZ TF
ZHENG SQ
Citation: Tf. Gonzalez et Sq. Zheng, ON ENSURING MULTILAYER WIRABILITY BY STRETCHING LAYOUTS, VLSI design (Print), 7(4), 1998, pp. 365-383
Authors:
CHANG RI
HSIAO PY
Citation: Ri. Chang et Py. Hsiao, MACROCELL PLACEMENT FOS CUSTOM-CHIP DESIGN USING SELF-ORGANIZING FUZZY TECHNIQUE, VLSI design (Print), 7(4), 1998, pp. 385-399
Authors:
CARCHIOLO V
MALGERI M
MANGIONI G
Citation: V. Carchiolo et al., FORMAL CODESIGN METHODOLOGY WITH MULTISTEP PARTITIONING, VLSI design (Print), 7(4), 1998, pp. 401-423
Authors:
MEHTA DP
Citation: Dp. Mehta, CLOTH MEASURE - A SOFTWARE TOOL FOR ESTIMATING THE MEMORY REQUIREMENTS OF CORNER STITCHING DATA-STRUCTURES, VLSI design (Print), 7(4), 1998, pp. 425-436
Authors:
RAVIKUMAR CP
JOSHI H
Citation: Cp. Ravikumar et H. Joshi, SCOAP-BASED TESTABILITY ANALYSIS FROM HIERARCHICAL NETLISTS, VLSI design (Yverdon), 7(2), 1998, pp. 131-141
Authors:
ACCIARO V
NAYAK A
Citation: V. Acciaro et A. Nayak, CHARACTERIZATION OF CATASTROPHIC FAULTS IN RECONFIGURABLE SYSTOLIC ARRAYS, VLSI design (Yverdon), 7(2), 1998, pp. 143-150
Authors:
BUSABA F
LALA PK
WALKER A
Citation: F. Busaba et al., ON SELF-CHECKING DESIGN OF CMOS CIRCUITS FOR MULTIPLE FAULTS, VLSI design (Yverdon), 7(2), 1998, pp. 151-161
Authors:
SPIEGEL G
STROELE AP
Citation: G. Spiegel et Ap. Stroele, REALISTIC FAULT MODELING AND EXTRACTION OF MULTIPLE BRIDGING AND BREAK FAULTS, VLSI design (Yverdon), 7(2), 1998, pp. 163-176
Authors:
KARAFYLLIDIS I
ANDREADIS I
TSALIDES P
THANAILAKIS A
Citation: I. Karafyllidis et al., NONLINEAR HYBRID CELLULAR-AUTOMATA AS PSEUDORANDOM PATTERN GENERATORSFOR VLSI SYSTEMS, VLSI design (Yverdon), 7(2), 1998, pp. 177-189
Authors:
DAS SR
GOEL N
JONE WB
NAYAK AR
Citation: Sr. Das et al., SYNDROME SIGNATURE IN OUTPUT COMPACTION FOR VLSI BUILT-IN SELF-TEST, VLSI design (Yverdon), 7(2), 1998, pp. 191-201
Authors:
ANDREADIS I
KOKOLAKIS I
GASTERATOS A
TSALIDES P
Citation: I. Andreadis et al., A STOCHASTIC D A CONVERTER BASED ON A CELLULAR-AUTOMATON ARCHITECTURE/, VLSI design (Yverdon), 7(2), 1998, pp. 203-210
Authors:
KARAYIANNIS D
TRAGOUDAS S
Citation: D. Karayiannis et S. Tragoudas, TIMING-DRIVEN CIRCUIT IMPLEMENTATION, VLSI design (Yverdon), 7(2), 1998, pp. 211-224
Authors:
CHO JD
Citation: Jd. Cho, SPECIAL ISSUE - HIGH-PERFORMANCE DESIGN AUTOMATION OF VLSI INTERCONNECTS - GUEST EDITORIAL, VLSI design, 7(1), 1998, pp. 1-3
Authors:
KARAYIANNIS D
TRAGOUDAS S
Citation: D. Karayiannis et S. Tragoudas, CLUSTERING NETWORK MODULES WITH DIFFERENT IMPLEMENTATIONS FOR DELAY MINIMIZATION, VLSI design, 7(1), 1998, pp. 1-13
Authors:
TELLEZ GE
SARRAFZADEH M
Citation: Ge. Tellez et M. Sarrafzadeh, ON RECTILINEAR DISTANCE-PRESERVING TREES (REPRINTED), VLSI design, 7(1), 1998, pp. 15-30