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Results: 1-25 | 26-38
Results: 1-25/38
A RATED-CLOCK TEST METHOD FOR PATH DELAY FAULTS
Authors: BOSE S AGRAWAL P AGRAWAL VD
Citation: S. Bose et al., A RATED-CLOCK TEST METHOD FOR PATH DELAY FAULTS, IEEE transactions on very large scale integration (VLSI) systems, 6(2), 1998, pp. 323-331
STATISTICAL DELAY-FAULT COVERAGE ESTIMATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS
Authors: PAPPU L BUSHNELL ML AGRAWAL VD MANDYAMKOMAR S
Citation: L. Pappu et al., STATISTICAL DELAY-FAULT COVERAGE ESTIMATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 12(3), 1998, pp. 239-254
SPECIAL ISSUE ON ONLINE TESTING
Authors: AGRAWAL VD
Citation: Vd. Agrawal, SPECIAL ISSUE ON ONLINE TESTING, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 12(1-2), 1998, pp. 5-5
A PARALLEL-VECTOR CONCURRENT-FAULT SIMULATOR AND GENERATION OF SINGLE-INPUT-CHANGE TESTS FOR PATH-DELAY FAULTS
Authors: GHARAYBEH MA BUSHNELL ML AGRAWAL VD
Citation: Ma. Gharaybeh et al., A PARALLEL-VECTOR CONCURRENT-FAULT SIMULATOR AND GENERATION OF SINGLE-INPUT-CHANGE TESTS FOR PATH-DELAY FAULTS, IEEE transactions on computer-aided design of integrated circuits and systems, 17(9), 1998, pp. 873-876
THE PATH-STATUS GRAPH WITH APPLICATION TO DELAY-FAULT SIMULATION
Authors: GHARAYBEH MA BUSHNELL ML AGRAWAL VD
Citation: Ma. Gharaybeh et al., THE PATH-STATUS GRAPH WITH APPLICATION TO DELAY-FAULT SIMULATION, IEEE transactions on computer-aided design of integrated circuits and systems, 17(4), 1998, pp. 324-332
DERIVING LOGIC SYSTEMS FOR PATH DELAY TEST-GENERATION
Authors: BOSE S AGARWAL P AGRAWAL VD
Citation: S. Bose et al., DERIVING LOGIC SYSTEMS FOR PATH DELAY TEST-GENERATION, I.E.E.E. transactions on computers, 47(8), 1998, pp. 829-846
SCHEDULING TESTS FOR VLSI SYSTEMS UNDER POWER CONSTRAINTS
Authors: CHOU RM SALUJA KK AGRAWAL VD
Citation: Rm. Chou et al., SCHEDULING TESTS FOR VLSI SYSTEMS UNDER POWER CONSTRAINTS, IEEE transactions on very large scale integration (VLSI) systems, 5(2), 1997, pp. 175-185
UNTITLED
Authors: AGRAWAL VD
Citation: Vd. Agrawal, UNTITLED, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 11(3), 1997, pp. 195-195
UNTITLED
Authors: AGRAWAL VD
Citation: Vd. Agrawal, UNTITLED, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 11(2), 1997, pp. 107-107
SPECIAL ISSUE ON TEST SYNTHESIS
Authors: AGRAWAL VD
Citation: Vd. Agrawal, SPECIAL ISSUE ON TEST SYNTHESIS, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 11(1), 1997, pp. 5-5
CLASSIFICATION AND TEST-GENERATION FOR PATH-DELAY FAULTS USING SINGLESTRUCK-AT FAULT-TESTS
Authors: GHARAYBEH MA BUSHNELL ML AGRAWAL VD
Citation: Ma. Gharaybeh et al., CLASSIFICATION AND TEST-GENERATION FOR PATH-DELAY FAULTS USING SINGLESTRUCK-AT FAULT-TESTS, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 11(1), 1997, pp. 55-67
SPECIAL ISSUE ON MULTICHIP-MODULE TESTING AND DESIGN FOR TESTABILITY
Authors: AGRAWAL VD
Citation: Vd. Agrawal, SPECIAL ISSUE ON MULTICHIP-MODULE TESTING AND DESIGN FOR TESTABILITY, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 10(1-2), 1997, pp. 5-5
IMPROVING A NONENUMERATIVE METHOD TO ESTIMATE PATH DELAY-FAULT COVERAGE
Authors: HERAGU K AGRAWAL VD BUSHNELL ML PATEL JH
Citation: K. Heragu et al., IMPROVING A NONENUMERATIVE METHOD TO ESTIMATE PATH DELAY-FAULT COVERAGE, IEEE transactions on computer-aided design of integrated circuits and systems, 16(7), 1997, pp. 759-762
ON VARIABLE CLOCK METHODS FOR PATH DELAY TESTING OF SEQUENTIAL-CIRCUITS
Authors: CHAKRABORTY TJ AGRAWAL VD BUSHNELL ML
Citation: Tj. Chakraborty et al., ON VARIABLE CLOCK METHODS FOR PATH DELAY TESTING OF SEQUENTIAL-CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 16(11), 1997, pp. 1237-1249
REDUNDANCY REMOVAL AND TEST-GENERATION FOR CIRCUITS WITH NON-BOOLEAN PRIMITIVES
Authors: CHAKRADHAR ST ROTHWEILER SG AGRAWAL VD
Citation: St. Chakradhar et al., REDUNDANCY REMOVAL AND TEST-GENERATION FOR CIRCUITS WITH NON-BOOLEAN PRIMITIVES, IEEE transactions on computer-aided design of integrated circuits and systems, 16(11), 1997, pp. 1370-1377
EDITORIAL
Authors: AGRAWAL VD
Citation: Vd. Agrawal, EDITORIAL, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 9(3), 1996, pp. 223-223
SPECIAL ISSUE ON ANALOG AND MIXED-SIGNAL TESTING
Authors: AGRAWAL VD
Citation: Vd. Agrawal, SPECIAL ISSUE ON ANALOG AND MIXED-SIGNAL TESTING, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 9(1-2), 1996, pp. 5-5
UNTITLED
Authors: AGRAWAL VD
Citation: Vd. Agrawal, UNTITLED, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 8(3), 1996, pp. 227-227
UNTITLED
Authors: AGRAWAL VD
Citation: Vd. Agrawal, UNTITLED, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 8(2), 1996, pp. 111-111
UNTITLED
Authors: AGRAWAL VD
Citation: Vd. Agrawal, UNTITLED, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 8(1), 1996, pp. 5-5
1995 ASIAN TEST SYMPOSIUM CARVES A NICHE
Authors: AGRAWAL VD
Citation: Vd. Agrawal, 1995 ASIAN TEST SYMPOSIUM CARVES A NICHE, IEEE design & test of computers, 13(2), 1996, pp. 3-3
FUNCTIONAL TEST-GENERATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS
Authors: SRINIVAS MK JACOB J AGRAWAL VD
Citation: Mk. Srinivas et al., FUNCTIONAL TEST-GENERATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 15(7), 1996, pp. 831-843
UNTITLED
Authors: AGRAWAL VD
Citation: Vd. Agrawal, UNTITLED, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 7(3), 1995, pp. 143-143
SPECIAL ISSUE ON PARTIAL SCAN METHODS
Authors: AGRAWAL VD
Citation: Vd. Agrawal, SPECIAL ISSUE ON PARTIAL SCAN METHODS, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 7(1-2), 1995, pp. 5-6
UNTITLED
Authors: AGRAWAL VD
Citation: Vd. Agrawal, UNTITLED, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 6(3), 1995, pp. 263-263
Risultati: 1-25 | 26-38