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Results:
1-15
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Results: 15
Authors:
DMELLO DR
GULAK PG
Citation: Dr. Dmello et Pg. Gulak, DESIGN APPROACHES TO FIELD-PROGRAMMABLE ANALOG INTEGRATED-CIRCUITS, Analog integrated circuits and signal processing, 17(1-2), 1998, pp. 7-34
Authors:
LOWE KS
GULAK PG
Citation: Ks. Lowe et Pg. Gulak, A JOINT GATE SIZING AND BUFFER INSERTION METHOD FOR OPTIMIZING DELAY AND POWER IN CMOS AND BICMOS COMBINATIONAL LOGIC, IEEE transactions on computer-aided design of integrated circuits and systems, 17(5), 1998, pp. 419-434
Authors:
GROSS WJ
GULAK PG
Citation: Wj. Gross et Pg. Gulak, SIMPLIFIED MAP ALGORITHM SUITABLE FOR IMPLEMENTATION OF TURBO DECODERS, Electronics Letters, 34(16), 1998, pp. 1577-1578
Authors:
SHEIKHOLESLAMI A
GULAK PG
Citation: A. Sheikholeslami et Pg. Gulak, A SURVEY OF BEHAVIORAL MODELING OF FERROELECTRIC CAPACITORS, IEEE transactions on ultrasonics, ferroelectrics, and frequency control, 44(4), 1997, pp. 917-924
Authors:
SCHULTZ KJ
GULAK PG
Citation: Kj. Schultz et Pg. Gulak, A NOTE ON ARCHITECTURES FOR LARGE-CAPACITY CAMS - REPLY, Integration, 22(1-2), 1997, pp. 173-176
Authors:
SCHULTZ KJ
GULAK PG
Citation: Kj. Schultz et Pg. Gulak, PHYSICAL PERFORMANCE LIMITS FOR SHARED BUFFER ATM SWITCHES, IEEE transactions on communications, 45(8), 1997, pp. 997-1007
Authors:
SCHULTZ KJ
GULAK PG
Citation: Kj. Schultz et Pg. Gulak, MULTICAST CONTENTION RESOLUTION WITH SINGLE-CYCLE WINDOWING USING CONTENT-ADDRESSABLE FIFOS, IEEE/ACM transactions on networking, 4(5), 1996, pp. 731-742
Authors:
SHEIKHOLESLAMI A
GULAK PG
Citation: A. Sheikholeslami et Pg. Gulak, TRANSIENT MODELING OF FERROELECTRIC CAPACITORS FOR NONVOLATILE MEMORIES, IEEE transactions on ultrasonics, ferroelectrics, and frequency control, 43(3), 1996, pp. 450-456
Authors:
SCHULTZ KJ
GULAK PG
Citation: Kj. Schultz et Pg. Gulak, FULLY PARALLEL INTEGRATED CAM RAM USING PRECLASSIFICATION TO ENABLE LARGE CAPACITIES/, IEEE journal of solid-state circuits, 31(5), 1996, pp. 689-699
Authors:
SHEIKHOLESLAMI A
GULAK PG
Citation: A. Sheikholeslami et Pg. Gulak, TRANSIENT MODELING OF FERROELECTRIC CAPACITORS FOR SEMICONDUCTOR MEMORIES, Microelectronic engineering, 29(1-4), 1995, pp. 141-144
Authors:
SCHULTZ KJ
GULAK PG
Citation: Kj. Schultz et Pg. Gulak, ARCHITECTURES FOR LARGE-CAPACITY CAMS, Integration, 18(2-3), 1995, pp. 151-171
Authors:
SCHULTZ KJ
GULAK PG
Citation: Kj. Schultz et Pg. Gulak, THROTTLED-BUFFER ASYNCHRONOUS SWITCH FOR ATM, IEICE transactions on communications, E77B(3), 1994, pp. 351-358
Authors:
FEYGIN G
GULAK PG
CHOW P
Citation: G. Feygin et al., MINIMIZING EXCESS CODE LENGTH AND VLSI COMPLEXITY IN THE MULTIPLICATION FREE APPROXIMATION OF ARITHMETIC CODING, Information processing & management, 30(6), 1994, pp. 805-816
Authors:
FEYGIN G
GULAK PG
CHOW P
Citation: G. Feygin et al., A MULTIPROCESSOR ARCHITECTURE FOR VITERBI DECODERS WITH LINEAR SPEEDUP, IEEE transactions on signal processing, 41(9), 1993, pp. 2907-2917
Authors:
FEYGIN G
GULAK PG
Citation: G. Feygin et Pg. Gulak, ARCHITECTURAL TRADEOFFS FOR SURVIVOR SEQUENCE MEMORY MANAGEMENT IN VITERBI DECODERS, IEEE transactions on communications, 41(3), 1993, pp. 425-429
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