Authors:
ACOSTA AJ
JIMENEZ R
BARRIGA A
BELLIDO MJ
VALENCIA M
HUERTAS JL
Citation: Aj. Acosta et al., DESIGN AND CHARACTERIZATION OF A CMOS VLSI SELF-TIMED MULTIPLIER ARCHITECTURE BASED ON A BIT-LEVEL PIPELINED-ARRAY STRUCTURE, IEE proceedings. Circuits, devices and systems, 145(4), 1998, pp. 247-253
Citation: I. Baturone et al., TOWARDS THE IC IMPLEMENTATION OF ADAPTIVE FUZZY-SYSTEMS, IEICE transactions on fundamentals of electronics, communications and computer science, E81A(9), 1998, pp. 1877-1885
Citation: D. Vazquez et al., A HIGH-Q BANDPASS FULLY DIFFERENTIAL SC FILTER WITH ENHANCED TESTABILITY, IEEE journal of solid-state circuits, 33(7), 1998, pp. 976-986
Authors:
BATURONE I
SANCHEZSOLANO S
BARRIGA A
HUERTAS JL
Citation: I. Baturone et al., IMPLEMENTATION OF CMOS FUZZY CONTROLLERS AS MIXED-SIGNAL INTEGRATED-CIRCUITS, IEEE transactions on fuzzy systems, 5(1), 1997, pp. 1-19
Authors:
JUANCHICO J
BELLIDO MJ
ACOSTA AJ
VALENCIA M
HUERTAS JL
Citation: J. Juanchico et al., ANALYSIS OF METASTABLE OPERATION IN A CMOS DYNAMIC D-LATCH, Analog integrated circuits and signal processing, 14(1-2), 1997, pp. 143-157
Citation: Mj. Avedillo et al., CONSTRAINED STATE ASSIGNMENT OF EASILY TESTABLE FSMS, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 6(1), 1995, pp. 133-138
Authors:
VALENCIA M
BELLIDO MJ
HUERTAS JL
ACOSTA AJ
SANCHEZSOLANO S
Citation: M. Valencia et al., MODULAR ASYNCHRONOUS ARBITER INSENSITIVE TO METASTABILITY, I.E.E.E. transactions on computers, 44(12), 1995, pp. 1456-1461
Authors:
MEDEIRO F
PEREZVERDU B
RODRIGUEZVAZQUEZ A
HUERTAS JL
Citation: F. Medeiro et al., A VERTICALLY INTEGRATED TOOL FOR AUTOMATED DESIGN OF SIGMA-DELTA MODULATORS, IEEE journal of solid-state circuits, 30(7), 1995, pp. 762-772
Citation: Mj. Avedillo et al., FSMTEST - SYNTHESIS FOR TESTABILITY AND TEST-GENERATION OF PLA-BASED FSM, IEE proceedings. Computers and digital techniques, 141(4), 1994, pp. 221-228
Citation: Mj. Avedillo et al., STATE MERGING AND STATE SPLITTING VIA STATE ASSIGNMENT - A NEW FSM SYNTHESIS ALGORITHM, IEE proceedings. Computers and digital techniques, 141(4), 1994, pp. 229-237
Authors:
MEDEIRO F
RODRIGUEZMACIAS R
FERNANDEZ FV
DOMINGUEZCASTRO R
HUERTAS JL
RODRIGUEZVAZQUEZ A
Citation: F. Medeiro et al., GLOBAL DESIGN OF ANALOG CELLS USING STATISTICAL OPTIMIZATION TECHNIQUES, Analog integrated circuits and signal processing, 6(3), 1994, pp. 179-195
Authors:
MEDEIRO F
RODRIGUEZMACIAS R
FERNANDEZ FV
DOMINGUEZCASTRO R
HUERTAS JL
RODRIGUEZVAZQUEZ A
Citation: F. Medeiro et al., GLOBAL DESIGN OF ANALOG CELLS USING STATISTICAL OPTIMIZATION TECHNIQUES, Analog integrated circuits and signal processing, 6(3), 1994, pp. 179-195
Citation: Jl. Huertas et K. Horninger, SPECIAL ISSUE ON THE 1993 EUROPEAN SOLID-STATE CIRCUITS CONFERENCE - FOREWORD, IEEE journal of solid-state circuits, 29(8), 1994, pp. 855-856
Authors:
ESPEJO S
RODRIGUEZVAZQUEZ A
DOMINGUEZCASTRO R
HUERTAS JL
SANCHEZSINENCIO E
Citation: S. Espejo et al., SMART-PIXEL CELLULAR NEURAL NETWORKS IN ANALOG CURRENT-MODE CMOS TECHNOLOGY, IEEE journal of solid-state circuits, 29(8), 1994, pp. 895-905
Authors:
RODRIGUEZVAZQUEZ A
ESPEJO S
DOMINGUEZCASTRO R
HUERTAS JL
SANCHEZSINENCIO E
Citation: A. Rodriguezvazquez et al., CURRENT-MODE TECHNIQUES FOR THE IMPLEMENTATION OF CONTINUOUS-TIME ANDDISCRETE-TIME CELLULAR NEURAL NETWORKS, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 40(3), 1993, pp. 132-146
Authors:
LINARESBARRANCO B
SANCHEZSINENCIO E
RODRIGUEZVAZQUEZ A
HUERTAS JL
Citation: B. Linaresbarranco et al., A CMOS ANALOG ADAPTIVE BAM WITH ON-CHIP LEARNING AND WEIGHT REFRESHING, IEEE transactions on neural networks, 4(3), 1993, pp. 445-455