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Results: 1-13 |
Results: 13
SCALING POSSIBILITY OF PZT CAPACITORS FOR HIGH-DENSITY AND LOW-VOLTAGE NVFRAM APPLICATION
Authors: KOBAYASHI SD TANABE N MAEJIMA Y HAYASHI Y KUNIO T
Citation: Sd. Kobayashi et al., SCALING POSSIBILITY OF PZT CAPACITORS FOR HIGH-DENSITY AND LOW-VOLTAGE NVFRAM APPLICATION, Integrated ferroelectrics, 17(1-4), 1997, pp. 81-88
ELECTRICAL CHARACTERIZATION OF SRBI2TA2O9 CAPACITORS FOR NONVOLATILE MEMORY OPERATION
Authors: AMANUMA K KUNIO T
Citation: K. Amanuma et T. Kunio, ELECTRICAL CHARACTERIZATION OF SRBI2TA2O9 CAPACITORS FOR NONVOLATILE MEMORY OPERATION, Integrated ferroelectrics, 16(1-4), 1997, pp. 175-182
LOW-VOLTAGE SWITCHING CHARACTERISTICS OF SRBI2TA2O9 CAPACITORS
Authors: AMANUMA K KUNIO T
Citation: K. Amanuma et T. Kunio, LOW-VOLTAGE SWITCHING CHARACTERISTICS OF SRBI2TA2O9 CAPACITORS, JPN J A P 1, 35(9B), 1996, pp. 5229-5231
ULTRAUNIFORM CHEMICAL-MECHANICAL POLISHING (CMP) USING A HYDRO CHUCK,FEATURED BY WAFER MOUNTING ON A QUARTZ GLASS PLATE WITH FULLY FLAT, WATER-SUPPORTED SURFACE
Authors: HAYASHI Y NAKAJIMA T KUNIO T
Citation: Y. Hayashi et al., ULTRAUNIFORM CHEMICAL-MECHANICAL POLISHING (CMP) USING A HYDRO CHUCK,FEATURED BY WAFER MOUNTING ON A QUARTZ GLASS PLATE WITH FULLY FLAT, WATER-SUPPORTED SURFACE, JPN J A P 1, 35(2B), 1996, pp. 1054-1059
LOW-RESISTANCE SELF-ALIGNED TI-SILICIDE TECHNOLOGY FOR SUB-QUARTER MICRON CMOS DEVICES
Authors: MOGAMI T WAKABAYASHI H SAITO Y TATSUMI T MATSUKI T KUNIO T
Citation: T. Mogami et al., LOW-RESISTANCE SELF-ALIGNED TI-SILICIDE TECHNOLOGY FOR SUB-QUARTER MICRON CMOS DEVICES, I.E.E.E. transactions on electron devices, 43(6), 1996, pp. 932-939
AN EFFECTIVE CHANNEL-LENGTH DETERMINATION METHOD FOR LDD MOSFETS
Authors: TAKEUCHI K KASAI N KUNIO T TERADA K
Citation: K. Takeuchi et al., AN EFFECTIVE CHANNEL-LENGTH DETERMINATION METHOD FOR LDD MOSFETS, I.E.E.E. transactions on electron devices, 43(4), 1996, pp. 580-587
A 60-NS 1-MB NONVOLATILE FERROELECTRIC MEMORY WITH A NONDRIVEN CELL PLATE LINE WRITE READ SCHEME/
Authors: KOIKE H OTSUKI T KIMURA T FUKUMA M HAYASHI Y MAEJIMA Y AMANUMA K TANABE N MATSUKI T SAITO S TAKEUCHI T KOBAYASHI S KUNIO T HASE T MIYASAKA Y SHOHATA N TAKADA M
Citation: H. Koike et al., A 60-NS 1-MB NONVOLATILE FERROELECTRIC MEMORY WITH A NONDRIVEN CELL PLATE LINE WRITE READ SCHEME/, IEEE journal of solid-state circuits, 31(11), 1996, pp. 1625-1634
AMMONIUM-SALT-ADDED SILICA SLURRY FOR THE CHEMICAL-MECHANICAL POLISHING OF THE INTERLAYER DIELECTRIC FILM PLANARIZATION IN ULSIS
Authors: HAYASHI Y SAKURAI M NAKAJIMA T HAYASHI K SASAKI S CHIKAKI S KUNIO T
Citation: Y. Hayashi et al., AMMONIUM-SALT-ADDED SILICA SLURRY FOR THE CHEMICAL-MECHANICAL POLISHING OF THE INTERLAYER DIELECTRIC FILM PLANARIZATION IN ULSIS, JPN J A P 1, 34(2B), 1995, pp. 1037-1042
0.15 MU-M CMOS DEVICES WITH REDUCED JUNCTION CAPACITANCE
Authors: TANABE A TAKEUCHI K YAMAMOTO T MATSUKI T KUNIO T FUKUMA M NAKAJIMA K AIZAKI N MIYAMOTO H IKAWA E
Citation: A. Tanabe et al., 0.15 MU-M CMOS DEVICES WITH REDUCED JUNCTION CAPACITANCE, IEICE transactions on electronics, E78C(3), 1995, pp. 267-273
1.9-V OPERATED 0.15-MU-M CMOS WITH REDUCED JUNCTION CAPACITANCE
Authors: TAKEUCHI K TANABE A YAMAMOTO T MATSUKI T KUNIO T
Citation: K. Takeuchi et al., 1.9-V OPERATED 0.15-MU-M CMOS WITH REDUCED JUNCTION CAPACITANCE, NEC research & development, 36(1), 1995, pp. 105-113
HYBRID STRESS-ANALYSIS OF VISCOELASTIC BODY USING PHOTOVISCOELASTIC BIREFRINGENCE
Authors: MATSUMOTO S SUGIMORI S MIYANO Y KUNIO T
Citation: S. Matsumoto et al., HYBRID STRESS-ANALYSIS OF VISCOELASTIC BODY USING PHOTOVISCOELASTIC BIREFRINGENCE, JSME international journal. Series A, mechanics and material engineering, 37(3), 1994, pp. 303-306
TIN AS A PHOSPHORUS OUTDIFFUSION BARRIER LAYER FOR WSIX DOPED-POLYSILICON STRUCTURES
Authors: DRYNAN JM HADA H KUNIO T
Citation: Jm. Drynan et al., TIN AS A PHOSPHORUS OUTDIFFUSION BARRIER LAYER FOR WSIX DOPED-POLYSILICON STRUCTURES, IEICE transactions on electronics, E76C(4), 1993, pp. 613-625
A 30-NS 256-MB DRAM WITH A MULTIDIVIDED ARRAY STRUCTURE
Authors: SUGIBAYASHI T TAKESHIMA T NARITAKE I MATANO T TAKADA H AIMOTO Y FURUTA K FUJITA M SAEKI T SUGAWARA H MUROTANI T KASAI N SHIBAHARA K NAKAJIMA K HADA H HAMADA T AIZAKI N KUNIO T KAKEHASHI E MASUMORI K TANIGAWA T
Citation: T. Sugibayashi et al., A 30-NS 256-MB DRAM WITH A MULTIDIVIDED ARRAY STRUCTURE, IEEE journal of solid-state circuits, 28(11), 1993, pp. 1092-1098
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