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Results:
1-8
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Results: 8
Authors:
Bakalis, D
Kavousianos, X
Vergos, HT
Nikolos, D
Alexiou, GP
Citation: D. Bakalis et al., Low power built-in self-test schemes for array and booth multipliers, VLSI DESIGN, 12(3), 2001, pp. 431-448
Authors:
Vergos, HT
Tsiatouhas, Y
Haniotakis, T
Nikolos, D
Nicolaidis, M
Citation: Ht. Vergos et al., Path delay fault testing of multiplexer-based shifters, INT J ELECT, 88(8), 2001, pp. 923-937
Authors:
Kavousianos, X
Nikolos, D
Sidiropoulos, G
Citation: X. Kavousianos et al., Novel single and double output TSC CMOS checkers for m-out-of-n codes, VLSI DESIGN, 11(1), 2000, pp. 35-45
Authors:
Kalampoukas, L
Nikolos, D
Efstathiou, C
Vergos, HT
Kalamatianos, J
Citation: L. Kalampoukas et al., High-speed parallel-prefix module 2(n)-1 adders, IEEE COMPUT, 49(7), 2000, pp. 673-680
Authors:
Voyiatzis, I
Paschalis, A
Nikolos, D
Halatsis, C
Citation: I. Voyiatzis et al., An accumulator-based BIST approach for two-pattern testing, J ELEC TEST, 15(3), 1999, pp. 267-278
Authors:
Kavousianos, X
Nikolos, D
Foukarakis, G
Gnardellis, T
Citation: X. Kavousianos et al., New efficient totally self-checking Berger code checkers, INTEGRATION, 28(1), 1999, pp. 101-118
Authors:
Gizopoulos, D
Paschalis, A
Nikolos, D
Halatsis, C
Citation: D. Gizopoulos et al., On robust two-pattern testing of one-dimensional CMOS iterative logic arrays, INT J ELECT, 86(8), 1999, pp. 967-978
Authors:
Nikolos, D
Vergos, HT
Citation: D. Nikolos et Ht. Vergos, On the yield of VLSI processors with on-chip CPU cache, IEEE COMPUT, 48(10), 1999, pp. 1138-1144
Risultati:
1-8
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