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Results: 1-8 |
Results: 8
A 6.93-MU-M(2) FULL CMOS SRAM CELL TECHNOLOGY FOR 1.8-V HIGH-PERFORMANCE CACHE MEMORY
Authors: MINAMI M OHKI N ISHIDA H YAMANAKA T SHIMIZU A ISHIBASHI K SATOH A KURE T NISHIDA T NAGANO T
Citation: M. Minami et al., A 6.93-MU-M(2) FULL CMOS SRAM CELL TECHNOLOGY FOR 1.8-V HIGH-PERFORMANCE CACHE MEMORY, IEICE transactions on electronics, E80C(4), 1997, pp. 590-596
IMPACT OF HIGH-TEMPERATURE RAPID THERMAL ANNEALING IN DEEP-SUBMICROMETER CMOSFET DESIGN
Authors: SHIMIZU A OHKI N ISHIDA H YAMANAKA T KIKUSHIMA K OKUYAMA K KUBOTA K KOIKE A
Citation: A. Shimizu et al., IMPACT OF HIGH-TEMPERATURE RAPID THERMAL ANNEALING IN DEEP-SUBMICROMETER CMOSFET DESIGN, Electronics & communications in Japan. Part 2, Electronics, 79(12), 1996, pp. 54-63
A 1-V, 100-MHZ, 10-MW CACHE USING A SEPARATED BIT-LINE MEMORY-HIERARCHY ARCHITECTURE AND DOMINO TAG COMPARATORS
Authors: MIZUNO H MATSUZAKI N OSADA K SHINBO T OHKI N ISHIDA H ISHIBASHI K KURE T
Citation: H. Mizuno et al., A 1-V, 100-MHZ, 10-MW CACHE USING A SEPARATED BIT-LINE MEMORY-HIERARCHY ARCHITECTURE AND DOMINO TAG COMPARATORS, IEEE journal of solid-state circuits, 31(11), 1996, pp. 1618-1624
A 6-NS 4-MB CMOS SRAM WITH OFFSET-VOLTAGE-INSENSITIVE CURRENT SENSE AMPLIFIERS
Authors: ISHIBASHI K TAKASUGI K KOMIYAJI K TOYOSHIMA H YAMANAKA T FUKAMI A HASHIMOTO N OHKI N SHIMIZU A HASHIMOTO T NAGANO T NISHIDA T
Citation: K. Ishibashi et al., A 6-NS 4-MB CMOS SRAM WITH OFFSET-VOLTAGE-INSENSITIVE CURRENT SENSE AMPLIFIERS, IEICE transactions on electronics, E78C(6), 1995, pp. 728-734
ADVANCED TFT SRAM CELL TECHNOLOGY USING A PHASE-SHIFT LITHOGRAPHY
Authors: YAMANAKA T HASHIMOTO T HASEGAWA N TANAKA T HASHIMOTO N SHIMIZU A OHKI N ISHIBASHI K SASAKI K NISHIDA T MINE T TAKEDA E NAGANO T
Citation: T. Yamanaka et al., ADVANCED TFT SRAM CELL TECHNOLOGY USING A PHASE-SHIFT LITHOGRAPHY, I.E.E.E. transactions on electron devices, 42(7), 1995, pp. 1305-1313
A 6-NS 4-MB CMOS SRAM WITH OFFSET-VOLTAGE-INSENSITIVE CURRENT SENSE AMPLIFIERS
Authors: ISHIBASHI K TAKASUGI K TOYOSHIMA H YAMANAKA T FUKAMI A HASHIMOTO N OHKI N SHIMIZU A HASHIMOTO T NAGANO T NISHIDA T
Citation: K. Ishibashi et al., A 6-NS 4-MB CMOS SRAM WITH OFFSET-VOLTAGE-INSENSITIVE CURRENT SENSE AMPLIFIERS, IEEE journal of solid-state circuits, 30(4), 1995, pp. 480-486
A 300-MHZ 4-MB WAVE-PIPELINE CMOS SRAM USING A MULTIPHASE PLL
Authors: ISHIBASHI K KOMIYAJI K TOYOSHIMA H MINAMI M OHKI N ISHIDA H YAMANAKA T NAGANO T NISHIDA T
Citation: K. Ishibashi et al., A 300-MHZ 4-MB WAVE-PIPELINE CMOS SRAM USING A MULTIPHASE PLL, IEEE journal of solid-state circuits, 30(11), 1995, pp. 1189-1195
A 16-MB CMOS SRAM WITH A 2.3-MU-M(2) SINGLE-BIT-LINE MEMORY CELL
Authors: SASAKI K UEDA K TAKASUGI K TOYOSHIMA H ISHIBASHI K YAMANAKA T HASHIMOTO N OHKI N
Citation: K. Sasaki et al., A 16-MB CMOS SRAM WITH A 2.3-MU-M(2) SINGLE-BIT-LINE MEMORY CELL, IEEE journal of solid-state circuits, 28(11), 1993, pp. 1125-1130
Risultati: 1-8 |