AAAAAA

   
Results: 1-16 |
Results: 16
DESIGN CONSIDERATIONS FOR DIRECT-CONVERSION RECEIVERS
Authors: RAZAVI B
Citation: B. Razavi, DESIGN CONSIDERATIONS FOR DIRECT-CONVERSION RECEIVERS, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 44(6), 1997, pp. 428-435
RECENT ADVANCES IN RF INTEGRATED-CIRCUITS
Authors: RAZAVI B
Citation: B. Razavi, RECENT ADVANCES IN RF INTEGRATED-CIRCUITS, IEEE communications magazine, 35(12), 1997, pp. 36-43
A 2-GHZ 1.6-MW PHASE-LOCKED LOOP
Authors: RAZAVI B
Citation: B. Razavi, A 2-GHZ 1.6-MW PHASE-LOCKED LOOP, IEEE journal of solid-state circuits, 32(5), 1997, pp. 730-735
CHALLENGES IN PORTABLE RF TRANSCEIVER DESIGN
Authors: RAZAVI B
Citation: B. Razavi, CHALLENGES IN PORTABLE RF TRANSCEIVER DESIGN, IEEE circuits and devices magazine, 12(5), 1996, pp. 12-25
A 2.5-GB S 15-MW CLOCK RECOVERY CIRCUIT
Authors: RAZAVI B
Citation: B. Razavi, A 2.5-GB S 15-MW CLOCK RECOVERY CIRCUIT, IEICE transactions on electronics, E79C(7), 1996, pp. 883-891
A 2.5-GB S 15-MW CLOCK RECOVERY CIRCUIT
Authors: RAZAVI B
Citation: B. Razavi, A 2.5-GB S 15-MW CLOCK RECOVERY CIRCUIT, IEEE journal of solid-state circuits, 31(4), 1996, pp. 472-480
STUDY OF PHASE NOISE IN CMOS OSCILLATORS
Authors: RAZAVI B
Citation: B. Razavi, STUDY OF PHASE NOISE IN CMOS OSCILLATORS, IEEE journal of solid-state circuits, 31(3), 1996, pp. 331-343
A HIGH-PERFORMANCE SUPER SELF-ALIGNED 3-V 5-V BICMOS TECHNOLOGY WITH EXTREMELY LOW PARASITICS FOR LOW-POWER MIXED-SIGNAL APPLICATIONS/
Authors: SUNG JM CHIU TY LAU K LIU TM ARCHER VD RAZAVI B SWARTZ RG ERCEG FM GLICK JT HOWER GR KRAFTY SA LADUCA AJ LING MP MOERSCHEL KG POSSANZA WA PROZONIC MA LONG TP
Citation: Jm. Sung et al., A HIGH-PERFORMANCE SUPER SELF-ALIGNED 3-V 5-V BICMOS TECHNOLOGY WITH EXTREMELY LOW PARASITICS FOR LOW-POWER MIXED-SIGNAL APPLICATIONS/, I.E.E.E. transactions on electron devices, 42(3), 1995, pp. 513-522
DESIGN OF A 100-MHZ 10-MW 3-V SAMPLE-AND-HOLD AMPLIFIER IN DIGITAL BIPOLAR TECHNOLOGY
Authors: RAZAVI B
Citation: B. Razavi, DESIGN OF A 100-MHZ 10-MW 3-V SAMPLE-AND-HOLD AMPLIFIER IN DIGITAL BIPOLAR TECHNOLOGY, IEEE journal of solid-state circuits, 30(7), 1995, pp. 724-730
DESIGN OF HIGH-SPEED, LOW-POWER FREQUENCY-DIVIDERS AND PHASE-LOCKED LOOPS IN DEEP-SUBMICRON CMOS
Authors: RAZAVI B LEE KF YAN RH
Citation: B. Razavi et al., DESIGN OF HIGH-SPEED, LOW-POWER FREQUENCY-DIVIDERS AND PHASE-LOCKED LOOPS IN DEEP-SUBMICRON CMOS, IEEE journal of solid-state circuits, 30(2), 1995, pp. 101-109
A 200-MHZ 15-MW BICMOS SAMPLE-AND-HOLD AMPLIFIER WITH 3 V SUPPLY
Authors: RAZAVI B
Citation: B. Razavi, A 200-MHZ 15-MW BICMOS SAMPLE-AND-HOLD AMPLIFIER WITH 3 V SUPPLY, IEEE journal of solid-state circuits, 30(12), 1995, pp. 1326-1332
A 2-GHZ, 6-MW BICMOS FREQUENCY-SYNTHESIZER
Authors: AYTUR TS RAZAVI B
Citation: Ts. Aytur et B. Razavi, A 2-GHZ, 6-MW BICMOS FREQUENCY-SYNTHESIZER, IEEE journal of solid-state circuits, 30(12), 1995, pp. 1457-1462
IMPACT OF DISTRIBUTED GATE RESISTANCE ON THE PERFORMANCE OF MOS DEVICES
Authors: RAZAVI B YAN RH LEE KF
Citation: B. Razavi et al., IMPACT OF DISTRIBUTED GATE RESISTANCE ON THE PERFORMANCE OF MOS DEVICES, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 41(11), 1994, pp. 750-754
DESIGN TECHNIQUES FOR LOW-VOLTAGE HIGH-SPEED DIGITAL BIPOLAR CIRCUITS
Authors: RAZAVI B OTA Y SWARTZ RG
Citation: B. Razavi et al., DESIGN TECHNIQUES FOR LOW-VOLTAGE HIGH-SPEED DIGITAL BIPOLAR CIRCUITS, IEEE journal of solid-state circuits, 29(3), 1994, pp. 332-339
A 6-GHZ 60-MW BICMOS PHASE-LOCKED LOOP
Authors: RAZAVI B SUNG JJ
Citation: B. Razavi et Jj. Sung, A 6-GHZ 60-MW BICMOS PHASE-LOCKED LOOP, IEEE journal of solid-state circuits, 29(12), 1994, pp. 1560-1565
SPECIAL ISSUE ON ANALOG AND SIGNAL-PROCESSING CIRCUITS - FOREWORD
Authors: RAZAVI B SAMUELI H
Citation: B. Razavi et H. Samueli, SPECIAL ISSUE ON ANALOG AND SIGNAL-PROCESSING CIRCUITS - FOREWORD, IEEE journal of solid-state circuits, 28(12), 1993, pp. 1178-1179
Risultati: 1-16 |