ACNP - Italian Periodicals Catalogue

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Results: 1-10 |

Results: 10

Untitled

Authors: Renovell, M

Citation: M. Renovell, Untitled, J ELEC TEST, 17(5), 2001, pp. 371-371

Optimizing sinusoidal histogram test for low cost ADC BIST

Authors: Azais, F Bernard, S Bertrand, Y Renovell, M

Citation: F. Azais et al., Optimizing sinusoidal histogram test for low cost ADC BIST, J ELEC TEST, 17(3-4), 2001, pp. 255-266

A discussion on test pattern generation for FPGA - Implemented circuits

Authors: Renovell, M Portal, JM Faure, P Figueras, J Zorian, Y

Citation: M. Renovell et al., A discussion on test pattern generation for FPGA - Implemented circuits, J ELEC TEST, 17(3-4), 2001, pp. 283-290

A low-cost BIST architecture for linear histogram testing of ADCs

Authors: Azais, F Bernard, S Bertrand, Y Renovell, M

Citation: F. Azais et al., A low-cost BIST architecture for linear histogram testing of ADCs, J ELEC TEST, 17(2), 2001, pp. 139-147

On the detectability of CMOS floating gate transistor faults

Authors: Ivanov, A Rafiq, S Renovell, M Azais, F Bertrand, Y

Citation: A. Ivanov et al., On the detectability of CMOS floating gate transistor faults, IEEE COMP A, 20(1), 2001, pp. 116-128

Testing the local interconnect resources of SRAM-Based FPGA's

Authors: Renovell, M Portal, JM Figueras, J Zorian, Y

Citation: M. Renovell et al., Testing the local interconnect resources of SRAM-Based FPGA's, J ELEC TEST, 16(5), 2000, pp. 513-520

Combining functional and structural approaches for switched-current circuit testing

Authors: Renovell, M Azais, F Bodin, JC Bertrand, Y

Citation: M. Renovell et al., Combining functional and structural approaches for switched-current circuit testing, J ELEC TEST, 16(3), 2000, pp. 259-267

An approach to minimize the test configuration for the logic cells of the Xilinx XC4000 FPGAs family

Authors: Renovell, M Portal, JM Figueras, J Zorian, Y

Citation: M. Renovell et al., An approach to minimize the test configuration for the logic cells of the Xilinx XC4000 FPGAs family, J ELEC TEST, 16(3), 2000, pp. 289-299

Detection of defects using fault model oriented test sequences

Authors: Renovell, M Azais, F Bertrand, Y

Citation: M. Renovell et al., Detection of defects using fault model oriented test sequences, J ELEC TEST, 14(1-2), 1999, pp. 13-22

SRAM-based FPGAs: Testing the embedded RAM modules

Authors: Renovell, M Portal, JM Figueras, J Zorian, Y

Citation: M. Renovell et al., SRAM-based FPGAs: Testing the embedded RAM modules, J ELEC TEST, 14(1-2), 1999, pp. 159-167

Risultati: 1-10 |