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Results: 1-9 |
Results: 9
A COMPACT MODEL FOR THE GROUNDED-GATE NMOS TRANSISTOR BEHAVIOR UNDER CDM ESD STRESS
Authors: RUSS C VERHAEGE K BOCK K ROUSSEL PJ GROESENEKEN G MAES HE
Citation: C. Russ et al., A COMPACT MODEL FOR THE GROUNDED-GATE NMOS TRANSISTOR BEHAVIOR UNDER CDM ESD STRESS, Journal of electrostatics, 42(4), 1998, pp. 351-381
COMPONENT LEVEL ESD TESTING
Authors: VERHAEGE K
Citation: K. Verhaege, COMPONENT LEVEL ESD TESTING, Microelectronics and reliability, 38(1), 1998, pp. 115-128
GROUNDED-GATE NMOS TRANSISTOR BEHAVIOR UNDER CDM ESD STRESS CONDITIONS
Authors: VERHAEGE K RUSS C LUCHIES JM GROESENEKEN G KUPER FG
Citation: K. Verhaege et al., GROUNDED-GATE NMOS TRANSISTOR BEHAVIOR UNDER CDM ESD STRESS CONDITIONS, I.E.E.E. transactions on electron devices, 44(11), 1997, pp. 1972-1980
JUSTIFICATIONS FOR REDUCING HBM AND MM ESD QUALIFICATION TEST TIME
Authors: VERHAEGE K ROBINSONHAHN D RUSS C FARRIS M SCANLON J LIN D VELTRI J GROESENEKEN G
Citation: K. Verhaege et al., JUSTIFICATIONS FOR REDUCING HBM AND MM ESD QUALIFICATION TEST TIME, Microelectronics and reliability, 36(11-12), 1996, pp. 1715-1718
SIMULATION STUDY FOR THE CDM ESD BEHAVIOR OF THE GROUNDED-GATE NMOS
Authors: RUSS C VERHAEGE K BOCK K GROESENEKEN G MAES HE
Citation: C. Russ et al., SIMULATION STUDY FOR THE CDM ESD BEHAVIOR OF THE GROUNDED-GATE NMOS, Microelectronics and reliability, 36(11-12), 1996, pp. 1739-1742
INFLUENCE OF TESTER, TEST METHOD, AND DEVICE TYPE ON CDM ESD TESTING
Authors: VERHAEGE K GROESENEKEN GV MAES HE EGGER P GIESER H
Citation: K. Verhaege et al., INFLUENCE OF TESTER, TEST METHOD, AND DEVICE TYPE ON CDM ESD TESTING, IEEE transactions on components, packaging, and manufacturing technology. Part A, 18(2), 1995, pp. 284-294
ESD PROTECTION ELEMENTS DURING HBM STRESS TESTS - FURTHER NUMERICAL AND EXPERIMENTAL RESULTS
Authors: RUSS C GIESER H VERHAEGE K
Citation: C. Russ et al., ESD PROTECTION ELEMENTS DURING HBM STRESS TESTS - FURTHER NUMERICAL AND EXPERIMENTAL RESULTS, Quality and reliability engineering international, 11(4), 1995, pp. 285-294
THE ESD PROTECTION MECHANISMS AND THE RELATED FAILURE MODES AND MECHANISMS OBSERVED IN SOI SNAPBACK NMOSFETS
Authors: VERHAEGE K GROESENEKEN G COLINGE JP MAES HE
Citation: K. Verhaege et al., THE ESD PROTECTION MECHANISMS AND THE RELATED FAILURE MODES AND MECHANISMS OBSERVED IN SOI SNAPBACK NMOSFETS, Microelectronics and reliability, 35(3), 1995, pp. 555-566
DOUBLE SNAPBACK IN SOI NMOSFETS AND ITS APPLICATION FOR SOI ESD PROTECTION
Authors: VERHAEGE K GROESENEKEN G COLINGE JP MAES HE
Citation: K. Verhaege et al., DOUBLE SNAPBACK IN SOI NMOSFETS AND ITS APPLICATION FOR SOI ESD PROTECTION, IEEE electron device letters, 14(7), 1993, pp. 326-328
Risultati: 1-9 |