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Results: 276-300/339
Authors:
JONE WB
SHAH N
GLEASON A
DAS SR
Citation: Wb. Jone et al., PGEN - A NOVEL-APPROACH TO SEQUENTIAL-CIRCUIT TEST-GENERATION, VLSI design, 4(3), 1996, pp. 149-165
Authors:
MAJHI AK
JACOB J
PATNAIK LM
Citation: Ak. Majhi et al., A NOVEL PATH DELAY-FAULT SIMULATOR USING BINARY LOGIC, VLSI design, 4(3), 1996, pp. 167-179
Authors:
KIM K
SALUJA KK
Citation: K. Kim et Kk. Saluja, HYSIM - HYBRID FAULT SIMULATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS, VLSI design, 4(3), 1996, pp. 181-197
Authors:
EDIRISOORIYA G
Citation: G. Edirisooriya, CLOSED-FORM ALIASING PROBABILITY FOR Q-ARY SYMMETRICAL ERRORS, VLSI design, 4(3), 1996, pp. 199-205
Authors:
SRINIVAS M
PATNAIK LM
Citation: M. Srinivas et Lm. Patnaik, ON GENERATING OPTIMAL SIGNAL PROBABILITIES FOR RANDOM TESTS - A GENETIC APPROACH, VLSI design, 4(3), 1996, pp. 207-215
Authors:
VANDRIS E
SOBELMAN G
Citation: E. Vandris et G. Sobelman, SWITCH-LEVEL DIFFERENTIAL FAULT SIMULATION OF MOS VLSI CIRCUITS, VLSI design, 4(3), 1996, pp. 217-229
Authors:
MENON SM
MALAIYA YK
JAYASUMANA AP
Citation: Sm. Menon et al., FAULT MODELING OF ECL FOR HIGH FAULT COVERAGE OF PHYSICAL DEFECTS, VLSI design, 4(3), 1996, pp. 231-242
Authors:
BASU A
BANERJI DK
BASU A
WILSON TC
MAJITHIA JC
Citation: A. Basu et al., A MODIFIED APPROACH TO TEST PLAN GENERATION FOR COMBINATIONAL LOGIC BLOCKS, VLSI design, 4(3), 1996, pp. 243-256
Authors:
BANDYOPADHYAY S
SENGUPTA A
BHATTACHARYA BB
Citation: S. Bandyopadhyay et al., A METHODOLOGY FOR TESTING ARBITRARY BILATERAL BIT-LEVEL SYSTOLIC ARRAYS, VLSI design, 4(3), 1996, pp. 257-269
Authors:
JOZWIAK L
Citation: L. Jozwiak, GENERAL DECOMPOSITION AND ITS USE IN DIGITAL CIRCUIT SYNTHESIS (VOL 3, PG 225, 1995), VLSI design, 4(3), 1996, pp. 271-274
Authors:
MAHMOOD A
Citation: A. Mahmood, SPECIAL ISSUE ON HARDWARE ACCELERATORS FOR VLSI DESIGN, VLSI design, 4(2), 1996, pp. 1-2
Authors:
MAHMOOD A
BAKER WI
Citation: A. Mahmood et Wi. Baker, AN EVALUATION OF PARALLEL SYNCHRONOUS AND CONSERVATIVE ASYNCHRONOUS LOGIC-LEVEL SIMULATIONS, VLSI design, 4(2), 1996, pp. 91-105
Authors:
FEHR ES
SZYGENDA SA
OTT GE
Citation: Es. Fehr et al., AN INTEGRATED HARDWARE ARRAY FOR VERY HIGH-SPEED LOGIC SIMULATION, VLSI design, 4(2), 1996, pp. 107-118
Authors:
KANG S
HUR Y
SZYGENDA SA
Citation: S. Kang et al., A HARDWARE ACCELERATOR FOR FAULT SIMULATION UTILIZING A RECONFIGURABLE ARRAY ARCHITECTURE, VLSI design, 4(2), 1996, pp. 119-133
Authors:
HOWARD NJ
TYRRELL AM
ALLINSON NM
Citation: Nj. Howard et al., THE USE OF FIELD-PROGRAMMABLE GATE ARRAYS FOR THE HARDWARE ACCELERATION OF DESIGN AUTOMATION TASKS, VLSI design, 4(2), 1996, pp. 135-139
Authors:
KIM S
SRIDHAR R
Citation: S. Kim et R. Sridhar, HARDWARE DESIGN RULE CHECKER USING A CAM ARCHITECTURE, VLSI design, 4(2), 1996, pp. 141-147
Authors:
BHATIA D
CHOWDHARY A
Citation: D. Bhatia et A. Chowdhary, A MULTITERMINAL NET ROUTER FOR FIELD-PROGRAMMABLE GATE ARRAYS, VLSI design, 4(1), 1996, pp. 1-10
Authors:
YAN JT
HSIAO PY
Citation: Jt. Yan et Py. Hsiao, AN O(NLOGN) ALGORITHM FOR REGION DEFINITION USING CHANNELS SWITCHBOXES AND ORDERING ASSIGNMENT, VLSI design, 4(1), 1996, pp. 11-16
Authors:
HSIAO PY
Citation: Py. Hsiao, NEARLY BALANCED QUAD LIST QUAD TREE - A DATA STRUCTURE FOR VLSI LAYOUT SYSTEMS, VLSI design, 4(1), 1996, pp. 17-32
Authors:
BHAGAVATHI D
GURLA H
OLARIU S
SCHWING JL
ZHANG J
Citation: D. Bhagavathi et al., TIME-OPTIMAL AND COST-OPTIMAL PARALLEL ALGORITHMS FOR THE DOMINANCE AND VISIBILITY GRAPHS, VLSI design, 4(1), 1996, pp. 33-40
Authors:
HUANG JS
CHIN YH
Citation: Js. Huang et Yh. Chin, AN EFFICIENT ALGORITHM FOR THE SPLIT K-LAYER CIRCULAR TOPOLOGICAL VIAMINIMIZATION PROBLEM, VLSI design, 4(1), 1996, pp. 41-51
Authors:
CHOPRA S
TALLURI KT
Citation: S. Chopra et Kt. Talluri, MINIMUM-COST NODE-DISJOINT STEINER TREES IN SERIES-PARALLEL NETWORKS, VLSI design, 4(1), 1996, pp. 53-57
Authors:
MAHMOOD A
Citation: A. Mahmood, BEHAVIORAL SIMULATION AND PERFORMANCE EVALUATION OF MULTIPROCESSOR ARCHITECTURES, VLSI design, 4(1), 1996, pp. 59-68
Authors:
SRIVASTAVA A
PALAVALI SR
Citation: A. Srivastava et Sr. Palavali, INTEGRATION OF SPICE WITH TEK LV500 ASIC DESIGN VERIFICATION SYSTEM, VLSI design, 4(1), 1996, pp. 69-74
Authors:
SRIVASTAVA A
VENKATAPATHY K
Citation: A. Srivastava et K. Venkatapathy, DESIGN AND IMPLEMENTATION OF A LOW-POWER TERNARY FULL ADDER, VLSI design, 4(1), 1996, pp. 75-81