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Results: 101-125/339
Authors:
Falkowski, BJ
Chang, CH
Citation: Bj. Falkowski et Ch. Chang, An efficient algorithm for the calculation of Generalized Adding and Arithmetic transforms from disjoint cubes of Boolean functions, VLSI DESIGN, 9(2), 1999, pp. 135-146
Authors:
Theodoridis, G
Theoharis, S
Soudris, D
Goutis, C
Citation: G. Theodoridis et al., A new method for low power design of two-level logic circuits, VLSI DESIGN, 9(2), 1999, pp. 147-157
Authors:
Kim, JT
Kurdahi, FJ
Park, NB
Citation: Jt. Kim et al., System-level time-stationary control synthesis for pipelined data paths, VLSI DESIGN, 9(2), 1999, pp. 159-180
Authors:
Baraona, P
Alexander, P
Citation: P. Baraona et P. Alexander, Abstract architecture representation using VSPEC, VLSI DESIGN, 9(2), 1999, pp. 181-201
Authors:
Srivastava, A
Citation: A. Srivastava, Influence of BJT transit frequency limit relation to MOSFET parameters on the switching speed of BiCMOS digital circuits, VLSI DESIGN, 9(2), 1999, pp. 203-211
Authors:
Habib, SED
Al-Karim, GJ
Citation: Sed. Habib et Gj. Al-karim, An initialization technique for the waveform-relaxation circuit simulation, VLSI DESIGN, 9(2), 1999, pp. 213-218
Authors:
Lai, TH
Sheng, MJ
Citation: Th. Lai et Mj. Sheng, Sorting on reconfigurable meshes: An irregular decomposition approach, VLSI DESIGN, 9(1), 1999, pp. 1-16
Authors:
Ben-Asher, Y
Schuster, A
Citation: Y. Ben-asher et A. Schuster, Single step undirected reconfigurable networks, VLSI DESIGN, 9(1), 1999, pp. 17-28
Authors:
Ziavras, SG
Citation: Sg. Ziavras, Investigation of various mesh architectures with broadcast buses for high-performance computing, VLSI DESIGN, 9(1), 1999, pp. 29-54
Authors:
Chen, HN
Chung, KL
Citation: Hn. Chen et Kl. Chung, Partitionable bus-based string-matching algorithm for run-length coded strings with VLDCs, VLSI DESIGN, 9(1), 1999, pp. 55-67
Multiplication of matrices with different sparseness properties on dynamically reconfigurable meshes
Authors:
Middendorf, M
Schmeck, H
Schroder, H
Turner, G
Citation: M. Middendorf et al., Multiplication of matrices with different sparseness properties on dynamically reconfigurable meshes, VLSI DESIGN, 9(1), 1999, pp. 69-81
Authors:
Lin, R
Olariu, S
Citation: R. Lin et S. Olariu, Reconfigurable shift switching parallel comparators, VLSI DESIGN, 9(1), 1999, pp. 83-90
Authors:
Lim, JS
Iyengar, SS
Zheng, SQ
Citation: Js. Lim et al., Finding combined L-1 and link metric shortest paths in the presence of orthogonal obstacles: A heuristic approach, VLSI DESIGN, 9(1), 1999, pp. 91-104
Authors:
Olariu, S
Lin, R
Citation: S. Olariu et R. Lin, High-performance bus-based architectures - Guest editorial, VLSI DESIGN, 9(1), 1999, pp. I-II
Authors:
Stroele, AP
Citation: Ap. Stroele, Signature analysis for test responses of sequential circuits, VLSI DESIGN, 10(2), 1999, pp. 127-141
Authors:
Wu, WJ
Tang, CY
Citation: Wj. Wu et Cy. Tang, Automatic test timing assignment for RAMs using linear programming, VLSI DESIGN, 10(2), 1999, pp. 143-153
Authors:
Yan, JT
Citation: Jt. Yan, Routability crossing distribution and floating pin assignment for T-type junction region, VLSI DESIGN, 10(2), 1999, pp. 155-167
Authors:
Yan, JT
Citation: Jt. Yan, An ILP formulation for minimizing the number of feedthrough cells in a standard cell placement, VLSI DESIGN, 10(2), 1999, pp. 169-176
Authors:
Masselos, K
Merakos, P
Stouraitis, T
Goutis, CE
Citation: K. Masselos et al., Computation reordering: A novel transformation for low power DSP synthesis, VLSI DESIGN, 10(2), 1999, pp. 177-202
Authors:
John, LK
Citation: Lk. John, Memory chips with adjustable configurations, VLSI DESIGN, 10(2), 1999, pp. 203-215
Authors:
Ashenden, PJ
Wilsey, PA
Citation: Pj. Ashenden et Pa. Wilsey, Principles for language extensions to VHDL to support high-level modeling, VLSI DESIGN, 10(2), 1999, pp. 217-235
Authors:
Cheng, EYC
Sahni, S
Citation: Eyc. Cheng et S. Sahni, A fast algorithm for performance-driven module implementation selection, VLSI DESIGN, 10(2), 1999, pp. 237-247
Authors:
Stroobandt, D
Van Campenhout, J
Citation: D. Stroobandt et J. Van Campenhout, Accurate interconnection length estimations for predictions early in the design cycle, VLSI DESIGN, 10(1), 1999, pp. 1-20
Authors:
Kahng, AB
Muddu, S
Sarto, E
Citation: Ab. Kahng et al., Tuning strategies for global interconnects in high-performance deep-submicron ICs, VLSI DESIGN, 10(1), 1999, pp. 21-34
Authors:
Chrzanowska-Jeske, M
Xu, Y
Perkowski, M
Citation: M. Chrzanowska-jeske et al., Logic synthesis for a regular layout, VLSI DESIGN, 10(1), 1999, pp. 35-55