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Results: 1-25 | 26-27
Results: 1-25/27
BIPOLAR-FIELD-EFFECT-TRANSISTOR HYBRID-MODE OPERATION OF LATERAL SILICON-ON-INSULATOR BIPOLAR MODE FIELD-EFFECT TRANSISTOR WITH IMPROVED CURRENT GAIN
Authors: KIM DY KIM SD HAN MK CHOI YI
Citation: Dy. Kim et al., BIPOLAR-FIELD-EFFECT-TRANSISTOR HYBRID-MODE OPERATION OF LATERAL SILICON-ON-INSULATOR BIPOLAR MODE FIELD-EFFECT TRANSISTOR WITH IMPROVED CURRENT GAIN, JPN J A P 1, 37(4A), 1998, pp. 1787-1792
A COMPARISON OF POLY SILICON AND TITANIUM POLYCIDE FOR FIELD-EMISSIONTIP
Authors: PARK CM LIM MS HAN MK CHOI YI
Citation: Cm. Park et al., A COMPARISON OF POLY SILICON AND TITANIUM POLYCIDE FOR FIELD-EMISSIONTIP, JPN J A P 1, 37(4A), 1998, pp. 2021-2023
OBSERVATION OF RESONANCES BY INDIVIDUAL ENERGY-LEVELS IN INGAAS ALAS TRIPLE-BARRIER RESONANT-TUNNELING DIODES/
Authors: JO J CHOI YI KIM DM ALT K WANG KL
Citation: J. Jo et al., OBSERVATION OF RESONANCES BY INDIVIDUAL ENERGY-LEVELS IN INGAAS ALAS TRIPLE-BARRIER RESONANT-TUNNELING DIODES/, JPN J A P 1, 37(3B), 1998, pp. 1654-1656
A NEW GRADUAL HOLE INJECTION DUAL-GATE LIGBT
Authors: LEE BH CHUN JH KIM SD BYEON DS LEE WO HAN MK CHOI YI
Citation: Bh. Lee et al., A NEW GRADUAL HOLE INJECTION DUAL-GATE LIGBT, IEEE electron device letters, 19(12), 1998, pp. 490-492
CB-BRT - A NEW BASE RESISTANCE-CONTROLLED THYRISTOR EMPLOYING A SELF-ALIGNED CORRUGATED P-BASE
Authors: BYEON DS LEE BH KIM DY HAN MK CHOI YI
Citation: Ds. Byeon et al., CB-BRT - A NEW BASE RESISTANCE-CONTROLLED THYRISTOR EMPLOYING A SELF-ALIGNED CORRUGATED P-BASE, IEEE electron device letters, 19(12), 1998, pp. 493-495
OPTIMUM DESIGN OF THE FIELD PLATE IN THE CYLINDRICAL P(- ANALYTICAL APPROACH()N JUNCTION )
Authors: YANG K BYEON DS HAN MK CHOI YI
Citation: K. Yang et al., OPTIMUM DESIGN OF THE FIELD PLATE IN THE CYLINDRICAL P(- ANALYTICAL APPROACH()N JUNCTION ), Solid-state electronics, 42(9), 1998, pp. 1651-1655
DUAL-GATE SHORTED ANODE SOI LATERAL INSULATED GATE BIPOLAR-TRANSISTORSUPPRESSING THE SNAP-BACK
Authors: LEE BH BYEON DS KIM DY LEE WO HAN MK CHOI YI
Citation: Bh. Lee et al., DUAL-GATE SHORTED ANODE SOI LATERAL INSULATED GATE BIPOLAR-TRANSISTORSUPPRESSING THE SNAP-BACK, JPN J A P 1, 36(3B), 1997, pp. 1663-1666
EFFECTS OF DRIFT REGION DOPING ON CURRENT CHARACTERISTICS IN SOI BMFETS
Authors: KIM SD KIM DY LIM MS HAN MK CHOI YI
Citation: Sd. Kim et al., EFFECTS OF DRIFT REGION DOPING ON CURRENT CHARACTERISTICS IN SOI BMFETS, Physica scripta. T, T69, 1997, pp. 181-184
COMPARISON OF LATERAL IGBT AND LATERAL EMITTER SWITCHED THYRISTOR WITH A PARTIAL BURIED OXIDE LAYER
Authors: YUN CM KIM JH HAN MK CHOI YI
Citation: Cm. Yun et al., COMPARISON OF LATERAL IGBT AND LATERAL EMITTER SWITCHED THYRISTOR WITH A PARTIAL BURIED OXIDE LAYER, Physica scripta. T, T69, 1997, pp. 341-344
THE BREAKDOWN VOLTAGE OF NEGATIVE CURVATURED P(+)N DIODES USING A SOILAYER
Authors: BYEON DS HAN MK CHOI YI
Citation: Ds. Byeon et al., THE BREAKDOWN VOLTAGE OF NEGATIVE CURVATURED P(+)N DIODES USING A SOILAYER, Solid-state electronics, 41(5), 1997, pp. 787-788
AN ANALYTICAL MODEL FOR MINIMUM DRIFT REGION LENGTH OF SOI RESURF DIODES
Authors: CHUNG SK HAN SY SHIN JC CHOI YI KIM SB
Citation: Sk. Chung et al., AN ANALYTICAL MODEL FOR MINIMUM DRIFT REGION LENGTH OF SOI RESURF DIODES, IEEE electron device letters, 17(1), 1996, pp. 22-24
NUMERICAL-ANALYSIS OF A NEW VERTICAL IGBT STRUCTURE WITH REDUCED JFETEFFECT
Authors: YUN CM KIM DY HAN MK CHOI YI
Citation: Cm. Yun et al., NUMERICAL-ANALYSIS OF A NEW VERTICAL IGBT STRUCTURE WITH REDUCED JFETEFFECT, Solid-state electronics, 39(8), 1996, pp. 1179-1183
AN ANALYTICAL MODEL OF THE BREAKDOWN VOLTAGE AND MINIMUM EPI LAYER LENGTH FOR RESURF PN DIODES
Authors: HAN SY NA JM CHOI YI SHIN JC CHUNG SK
Citation: Sy. Han et al., AN ANALYTICAL MODEL OF THE BREAKDOWN VOLTAGE AND MINIMUM EPI LAYER LENGTH FOR RESURF PN DIODES, Solid-state electronics, 39(8), 1996, pp. 1247-1248
CLOSED-FORM ANALYTICAL EXPRESSIONS FOR THE BREAKDOWN VOLTAGE OF GAAS PARALLEL-PLANE P(+)N JUNCTION IN (100), (110) AND (111) ORIENTATIONS
Authors: CHUNG YS HAN SY CHOI YI CHUNG SK
Citation: Ys. Chung et al., CLOSED-FORM ANALYTICAL EXPRESSIONS FOR THE BREAKDOWN VOLTAGE OF GAAS PARALLEL-PLANE P(+)N JUNCTION IN (100), (110) AND (111) ORIENTATIONS, Solid-state electronics, 39(11), 1996, pp. 1678-1680
ANALYTICAL SOLUTION OF THE BREAKDOWN VOLTAGE FOR 6H-SILICON CARBIDE P(+)N JUNCTION
Authors: BYEON DS HAN MK CHOI YI
Citation: Ds. Byeon et al., ANALYTICAL SOLUTION OF THE BREAKDOWN VOLTAGE FOR 6H-SILICON CARBIDE P(+)N JUNCTION, Journal of applied physics, 79(5), 1996, pp. 2796-2797
A NEW POWER MOSFET WITH SELF CURRENT LIMITING CAPABILITY
Authors: YUN CM HAN MK CHOI YI
Citation: Cm. Yun et al., A NEW POWER MOSFET WITH SELF CURRENT LIMITING CAPABILITY, International journal of electronics, 80(2), 1996, pp. 131-142
A TRENCH-GATE SILICON-ON-INSULATOR LATERAL INSULATED GATE BIPOLAR-TRANSISTOR WITH THE P(+) CATHODE WELL
Authors: LEE BH YUN CM BYEON DS HAN MK CHOI YI
Citation: Bh. Lee et al., A TRENCH-GATE SILICON-ON-INSULATOR LATERAL INSULATED GATE BIPOLAR-TRANSISTOR WITH THE P(+) CATHODE WELL, JPN J A P 1, 34(2B), 1995, pp. 854-859
LOW-LOSS SCHOTTKY RECTIFIER UTILIZING TRENCH SIDEWALL AS JUNCTION-BARRIER-CONTROLLED SCHOTTKY CONTACT
Authors: KIM HS KIM SD HAN MK CHOI YI
Citation: Hs. Kim et al., LOW-LOSS SCHOTTKY RECTIFIER UTILIZING TRENCH SIDEWALL AS JUNCTION-BARRIER-CONTROLLED SCHOTTKY CONTACT, JPN J A P 1, 34(2B), 1995, pp. 913-916
BREAKDOWN VOLTAGE ENHANCEMENT OF THE P-N-JUNCTION BY SELF-ALIGNED DOUBLE DIFFUSION PROCESS THROUGH A TAPERED SIO2 IMPLANT MASK
Authors: KIM HS KIM SD HAN MK YOON SN CHOI YI
Citation: Hs. Kim et al., BREAKDOWN VOLTAGE ENHANCEMENT OF THE P-N-JUNCTION BY SELF-ALIGNED DOUBLE DIFFUSION PROCESS THROUGH A TAPERED SIO2 IMPLANT MASK, IEEE electron device letters, 16(9), 1995, pp. 405-407
AN ACCURATE ON-RESISTANCE MODEL FOR LOW-VOLTAGE VDMOS DEVICES
Authors: KIM SD KIM IJ HAN MK CHOI YI
Citation: Sd. Kim et al., AN ACCURATE ON-RESISTANCE MODEL FOR LOW-VOLTAGE VDMOS DEVICES, Solid-state electronics, 38(2), 1995, pp. 345-350
AN ANALYTICAL METHOD FOR 2-DIMENSIONAL FIELD DISTRIBUTION OF A MOS STRUCTURE WITH A FINITE-FIELD PLATE
Authors: CHUNG SK YOO DC CHOI YI
Citation: Sk. Chung et al., AN ANALYTICAL METHOD FOR 2-DIMENSIONAL FIELD DISTRIBUTION OF A MOS STRUCTURE WITH A FINITE-FIELD PLATE, I.E.E.E. transactions on electron devices, 42(1), 1995, pp. 192-194
LATCH-UP SUPPRESSED INSULATED GATE BIPOLAR-TRANSISTOR BY THE DEEP P(-IMPLANTATION UNDER THE N(+) SOURCE() ION)
Authors: LEE BH YUN CM KIM HS HAN MK CHOI YI
Citation: Bh. Lee et al., LATCH-UP SUPPRESSED INSULATED GATE BIPOLAR-TRANSISTOR BY THE DEEP P(-IMPLANTATION UNDER THE N(+) SOURCE() ION), JPN J A P 1, 33(1B), 1994, pp. 563-566
CALCULATION OF AVALANCHE BREAKDOWN VOLTAGE OF THE INP P-N JUNCTION()
Authors: MOON TH CHOI YI CHUNG SK
Citation: Th. Moon et al., CALCULATION OF AVALANCHE BREAKDOWN VOLTAGE OF THE INP P-N JUNCTION(), Solid-state electronics, 37(1), 1994, pp. 187-188
ANALYTICAL EXPRESSIONS FOR THE 3-DIMENSIONAL EFFECT ON THE BREAKDOWN VOLTAGES OF PLANAR JUNCTIONS IN NONPUNCHTHROUGH AND PUNCHTHROUGH CASES
Authors: KKIM IJ KIM SD CHOI YI HAN MK
Citation: Ij. Kkim et al., ANALYTICAL EXPRESSIONS FOR THE 3-DIMENSIONAL EFFECT ON THE BREAKDOWN VOLTAGES OF PLANAR JUNCTIONS IN NONPUNCHTHROUGH AND PUNCHTHROUGH CASES, I.E.E.E. transactions on electron devices, 41(9), 1994, pp. 1661-1665
A POWER MOSFET DESIGN METHODOLOGY CONSIDERING EPI PARAMETER VARIATIONS
Authors: HWANG SK CHOI YI CHUNG SK LEE K KIM CK
Citation: Sk. Hwang et al., A POWER MOSFET DESIGN METHODOLOGY CONSIDERING EPI PARAMETER VARIATIONS, IEEE transactions on semiconductor manufacturing, 6(4), 1993, pp. 377-380
Risultati: 1-25 | 26-27