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Results: 1-9 |
Results: 9
Pi-gate SOI MOSFET
Authors: Park, JT Colinge, JP Diaz, CH
Citation: Jt. Park et al., Pi-gate SOI MOSFET, IEEE ELEC D, 22(8), 2001, pp. 405-406
Characterization of polysilicon resistors in sub-0.25 mu m CMOS ULSI applications
Authors: Liu, WC Thei, KB Chuang, HM Lin, KW Cheng, CC Ho, YS Su, CW Wong, SC Lin, CH Diaz, CH
Citation: Wc. Liu et al., Characterization of polysilicon resistors in sub-0.25 mu m CMOS ULSI applications, IEEE ELEC D, 22(7), 2001, pp. 318-320
An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling
Authors: Diaz, CH Tao, HJ Ku, YC Yen, A Young, K
Citation: Ch. Diaz et al., An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling, IEEE ELEC D, 22(6), 2001, pp. 287-289
Interface induced uphill diffusion of boron: An effective approach for ultrashallow junction
Authors: Wang, HCH Wang, CC Chang, CS Wang, TH Griffin, PB Diaz, CH
Citation: Hch. Wang et al., Interface induced uphill diffusion of boron: An effective approach for ultrashallow junction, IEEE ELEC D, 22(2), 2001, pp. 65-67
Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design
Authors: Kleveland, B Diaz, CH Vook, D Madden, L Lee, TH Wong, SS
Citation: B. Kleveland et al., Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design, IEEE J SOLI, 36(10), 2001, pp. 1480-1488
Application of technology CAD in process development for high performance logic and system-on-chip in IC foundry
Authors: Liew, BK Wang, CC Diaz, CH Wu, SY Sun, JYC Lin, YF Kuo, DS Lin, HT Yen, A
Citation: Bk. Liew et al., Application of technology CAD in process development for high performance logic and system-on-chip in IC foundry, IEICE TR EL, E83C(8), 2000, pp. 1275-1280
Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technology
Authors: Wang, HCH Diaz, CH Liew, BK Sun, JYC Wang, TH
Citation: Hch. Wang et al., Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technology, IEEE ELEC D, 21(12), 2000, pp. 598-600
The method to optimize gate oxide integrity, hot carrier effect and electro-static discharge without sacrificing the performance in sub-quarter micron dual gate oxide process
Authors: Shih, JR Lee, JH Chen, SH Wu, YH Diaz, CH Liew, BK Hwang, HL
Citation: Jr. Shih et al., The method to optimize gate oxide integrity, hot carrier effect and electro-static discharge without sacrificing the performance in sub-quarter micron dual gate oxide process, JPN J A P 2, 38(11B), 1999, pp. L1287-L1290
MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)
Authors: Choi, CH Goo, JS Oh, TY Yu, ZP Dutton, RW Bayoumi, A Cao, M Vande Voorde, P Vook, D Diaz, CH
Citation: Ch. Choi et al., MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm), IEEE ELEC D, 20(6), 1999, pp. 292-294
Risultati: 1-9 |