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Results: 1-11 |
Results: 11
Techniques for widening lock and pull-in ranges and suppressing jitter in clock and data recovery ICs - Duplicated loop control CDR
Authors: Kishine, K Ishihara, N Ichino, H
Citation: K. Kishine et al., Techniques for widening lock and pull-in ranges and suppressing jitter in clock and data recovery ICs - Duplicated loop control CDR, IEICE TR EL, E84C(4), 2001, pp. 460-469
10 Gigabit Ethernet technologies
Authors: Ishida, O Ichino, H
Citation: O. Ishida et H. Ichino, 10 Gigabit Ethernet technologies, NTT REVIEW, 13(4), 2001, pp. 42-47
A jitter suppression technique for a clock multiplier
Authors: Ishii, K Kishine, K Ichino, H
Citation: K. Ishii et al., A jitter suppression technique for a clock multiplier, IEICE TR EL, E83C(4), 2000, pp. 647-651
A 0.6-W 10-Gb/s SONET/SDH fit-error-rate monitoring LSI
Authors: Kawai, K Ichino, H
Citation: K. Kawai et H. Ichino, A 0.6-W 10-Gb/s SONET/SDH fit-error-rate monitoring LSI, IEEE J SOLI, 35(12), 2000, pp. 1988-1991
A compact MU-interface, 2,5-Gb/s optical transmitter module with LD-driverIC embedded in L-shaped wiring substrate
Authors: Ishitsuka, F Iwasaki, N Hirose, M Yanagibashi, M Ichino, H Ando, Y
Citation: F. Ishitsuka et al., A compact MU-interface, 2,5-Gb/s optical transmitter module with LD-driverIC embedded in L-shaped wiring substrate, IEEE T AD P, 22(3), 1999, pp. 451-459
Low-power 2.5-Gb/s Si-bipolar IC chipset for optical receivers and transmitters using low-voltage and adjustment-free circuit techniques
Authors: Hirose, M Kishine, K Ichino, H Ishihara, N
Citation: M. Hirose et al., Low-power 2.5-Gb/s Si-bipolar IC chipset for optical receivers and transmitters using low-voltage and adjustment-free circuit techniques, IEICE TR EL, E82C(3), 1999, pp. 511-518
An ultracompact, 2-cc-size, low-power 2.5-Gb/s optical receiver module incorporating an MU receptacle
Authors: Hirose, M Ishihara, N Akazawa, Y Ichino, H
Citation: M. Hirose et al., An ultracompact, 2-cc-size, low-power 2.5-Gb/s optical receiver module incorporating an MU receptacle, J LIGHTW T, 17(11), 1999, pp. 2349-2355
A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LAN'S and WAN's
Authors: Kishine, K Ishihara, N Takiguchi, K Ichino, H
Citation: K. Kishine et al., A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LAN'S and WAN's, IEEE J SOLI, 34(6), 1999, pp. 805-812
A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design
Authors: Kawai, K Koike, K Takei, Y Onozawa, A Obara, H Ichino, H
Citation: K. Kawai et al., A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design, IEEE J SOLI, 34(1), 1999, pp. 12-17
2.5 Gbit/s clock and data recovery circuit IC using novel duplicated PLL technique
Authors: Kishine, K Takiguchi, K Ichino, H
Citation: K. Kishine et al., 2.5 Gbit/s clock and data recovery circuit IC using novel duplicated PLL technique, ELECTR LETT, 35(5), 1999, pp. 360-361
250 mW 2.488 Gbit s and 622 Mbit s SONET SDH bit-error-monitoring LSI
Authors: Kawai, K Ichino, H
Citation: K. Kawai et H. Ichino, 250 mW 2.488 Gbit s and 622 Mbit s SONET SDH bit-error-monitoring LSI, ELECTR LETT, 35(11), 1999, pp. 914-916
Risultati: 1-11 |